From fb3b09db15e4f7faae74c969005afea0e9e9cce1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 10 Dec 2020 18:32:21 +0100 Subject: [PATCH] integration/soc/add_uart: add crossover+bridge support. Useful to have both CPU UART and bridge debug capability. --- litex/soc/integration/soc.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 92744b9f2..b0c66ed52 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1100,6 +1100,13 @@ class LiteXSoC(SoC): tx_fifo_depth = fifo_depth, rx_fifo_depth = fifo_depth) + # Crossover + Bridge + elif name in ["crossover+bridge"]: + self.add_uartbone(baudrate=baudrate) + self.submodules.uart = uart.UARTCrossover( + tx_fifo_depth = fifo_depth, + rx_fifo_depth = fifo_depth) + # Model/Sim elif name in ["model", "sim"]: self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))