From fb3e61230b71a0b1b72821683b43ae0bcda12f30 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 28 May 2013 15:56:14 +0200
Subject: [PATCH] Use new memory port API

---
 milkymist/dvisampler/chansync.py | 2 ++
 milkymist/dvisampler/edid.py     | 1 +
 top.py                           | 4 ++--
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
index 3a50b3d38..ce6bbaca1 100644
--- a/milkymist/dvisampler/chansync.py
+++ b/milkymist/dvisampler/chansync.py
@@ -21,6 +21,7 @@ class _SyncBuffer(Module):
 		self.specials += storage
 
 		wrport = storage.get_port(write_capable=True)
+		self.specials += wrport
 		self.comb += [
 			wrport.adr.eq(produce),
 			wrport.dat_w.eq(self.din),
@@ -29,6 +30,7 @@ class _SyncBuffer(Module):
 		self.sync += _inc(produce, depth)
 
 		rdport = storage.get_port(async_read=True)
+		self.specials += rdport
 		self.comb += [
 			rdport.adr.eq(consume),
 			self.dout.eq(rdport.dat_r)
diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py
index c2726a471..012a75308 100644
--- a/milkymist/dvisampler/edid.py
+++ b/milkymist/dvisampler/edid.py
@@ -89,6 +89,7 @@ class EDID(Module, AutoCSR):
 			)
 		]
 		rdport = self.mem.get_port()
+		self.specials += rdport
 		self.comb += rdport.adr.eq(offset_counter)
 		data_bit = Signal()
 
diff --git a/top.py b/top.py
index 1ab79e12d..6dbb0f541 100644
--- a/top.py
+++ b/top.py
@@ -86,8 +86,8 @@ class SoC(Module):
 		"uart":			0,
 		"timer0":		1,
 		"minimac":		2,
-		"dvisampler0":  3,
-		"dvisampler1":  4,
+		"dvisampler0":	3,
+		"dvisampler1":	4,
 	}
 
 	def __init__(self, platform):