From fbf03ec74c7d3c941e4db01f02a37ff7d58651fe Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 May 2024 10:36:07 +0200 Subject: [PATCH] inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it. Also cleanup self.mem.get_port call. --- litex/soc/interconnect/axi/axi_lite.py | 10 +++++++--- litex/soc/interconnect/wishbone.py | 10 +++++++--- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py index 6af6d715d..4e0b357a2 100644 --- a/litex/soc/interconnect/axi/axi_lite.py +++ b/litex/soc/interconnect/axi/axi_lite.py @@ -218,7 +218,8 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we= # AXI-Lite SRAM ------------------------------------------------------------------------------------ -class AXILiteSRAM(Module): +class AXILiteSRAM(LiteXModule): + autocsr_exclude = {"mem"} def __init__(self, mem_or_size, read_only=None, init=None, bus=None, name=None): if bus is None: bus = AXILiteInterface() @@ -240,8 +241,11 @@ class AXILiteSRAM(Module): # # # # Create memory port - port = self.mem.get_port(write_capable=not read_only, we_granularity=8, - mode=READ_FIRST if read_only else WRITE_FIRST) + port = self.mem.get_port( + write_capable = not read_only, + we_granularity = 8, + mode = READ_FIRST if read_only else WRITE_FIRST, + ) self.specials += self.mem, port # Generate write enable signal diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 4ef9e55ef..13df1bc60 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -450,7 +450,8 @@ class Converter(LiteXModule): # Wishbone SRAM ------------------------------------------------------------------------------------ -class SRAM(Module): # FIXME: Switch to LiteXModule. +class SRAM(LiteXModule): + autocsr_exclude = {"mem"} def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None): if bus is None: bus = Interface(data_width=32, address_width=32, addressing="word") @@ -545,8 +546,11 @@ class SRAM(Module): # FIXME: Switch to LiteXModule. # Memory. # ------- - port = self.mem.get_port(write_capable=not read_only, we_granularity=8, - mode=READ_FIRST if read_only else WRITE_FIRST) + port = self.mem.get_port( + write_capable = not read_only, + we_granularity = 8, + mode = READ_FIRST if read_only else WRITE_FIRST, + ) self.specials += self.mem, port # Generate write enable signal if not read_only: