From d5dab98a2cb8ae597a18c130832e15b075a1dfa9 Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Mon, 10 May 2021 19:59:38 +0200 Subject: [PATCH] Add CFU integration --- litex/soc/cores/cpu/vexriscv/core.py | 57 ++++++++++++++++++++++++++++ litex/soc/integration/soc_core.py | 10 +++++ 2 files changed, 67 insertions(+) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index fd2ad45fa..d55c6eb62 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -31,7 +31,9 @@ CPU_VARIANTS = { "imac": "VexRiscv_IMAC", "imac+debug": "VexRiscv_IMACDebug", "full": "VexRiscv_Full", + "full+cfu": "VexRiscv_FullCfu", "full+debug": "VexRiscv_FullDebug", + "full+cfu+debug": "VexRiscv_FullCfuDebug", "linux": "VexRiscv_Linux", "linux+debug": "VexRiscv_LinuxDebug", "linux+no-dsp": "VexRiscv_LinuxNoDspFmax", @@ -58,7 +60,9 @@ GCC_FLAGS = { "imac": "-march=rv32imac -mabi=ilp32", "imac+debug": "-march=rv32imac -mabi=ilp32", "full": "-march=rv32im -mabi=ilp32", + "full+cfu": "-march=rv32im -mabi=ilp32", "full+debug": "-march=rv32im -mabi=ilp32", + "full+cfu+debug": "-march=rv32im -mabi=ilp32", "linux": "-march=rv32ima -mabi=ilp32", "linux+debug": "-march=rv32ima -mabi=ilp32", "linux+no-dsp": "-march=rv32ima -mabi=ilp32", @@ -278,6 +282,59 @@ class VexRiscv(CPU, AutoCSR): self.external_variant = True self.platform.add_source(variant_filename) + def add_cfu(self, cfu_filename): + cfu_bus_layout = [ + ("cmd", [ + ("valid", 1), + ("ready", 1), + ("payload", [ + ("function_id", 10), + ("inputs_0", 32), + ("inputs_1", 32), + ]), + ]), + ("rsp", [ + ("valid", 1), + ("ready", 1), + ("payload", [ + ("response_ok", 1), + ("outputs_0", 32), + ]), + ]), + ] + + # CFU Bus. + self.cfu_bus = cfu_bus = Record(cfu_bus_layout) + + # Add CFU. + self.specials += Instance("Cfu", + i_cmd_valid = cfu_bus.cmd.valid, + o_cmd_ready = cfu_bus.cmd.ready, + i_cmd_payload_function_id = cfu_bus.cmd.payload.function_id, + i_cmd_payload_inputs_0 = cfu_bus.cmd.payload.inputs_0, + i_cmd_payload_inputs_1 = cfu_bus.cmd.payload.inputs_1, + o_rsp_valid = cfu_bus.rsp.valid, + i_rsp_ready = cfu_bus.rsp.ready, + o_rsp_payload_response_ok = cfu_bus.rsp.payload.response_ok, + o_rsp_payload_outputs_0 = cfu_bus.rsp.payload.outputs_0, + i_clk = ClockSignal(), + i_reset = ResetSignal(), + ) + self.platform.add_source(cfu_filename) + + # Connect CFU to CPU. + self.cpu_params.update( + o_CfuPlugin_bus_cmd_valid = cfu_bus.cmd.valid, + i_CfuPlugin_bus_cmd_ready = cfu_bus.cmd.ready, + o_CfuPlugin_bus_cmd_payload_function_id = cfu_bus.cmd.payload.function_id, + o_CfuPlugin_bus_cmd_payload_inputs_0 = cfu_bus.cmd.payload.inputs_0, + o_CfuPlugin_bus_cmd_payload_inputs_1 = cfu_bus.cmd.payload.inputs_1, + i_CfuPlugin_bus_rsp_valid = cfu_bus.rsp.valid, + o_CfuPlugin_bus_rsp_ready = cfu_bus.rsp.ready, + i_CfuPlugin_bus_rsp_payload_response_ok = cfu_bus.rsp.payload.response_ok, + i_CfuPlugin_bus_rsp_payload_outputs_0 = cfu_bus.rsp.payload.outputs_0, + ) + def do_finalize(self): assert hasattr(self, "reset_address") if not self.external_variant: diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index c75a0d956..6e4f39eb2 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -70,6 +70,8 @@ class SoCCore(LiteXSoC): cpu_reset_address = None, cpu_variant = None, cpu_cls = None, + # CFU parameters + cfu_filename = None, # ROM parameters integrated_rom_size = 0, integrated_rom_mode = "r", @@ -190,6 +192,11 @@ class SoCCore(LiteXSoC): if timer_uptime: self.timer0.add_uptime() + # Add CFU + if cfu_filename: + assert(cpu_type == "vexriscv") + self.cpu.add_cfu(cfu_filename=cfu_filename) + # Methods -------------------------------------------------------------------------------------- def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False): @@ -302,6 +309,9 @@ def soc_core_args(parser): # L2 Cache parser.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size (default=8192).") + # CFU + parser.add_argument("--cfu-filename", default=None, help="CFU verilog filename.") + def soc_core_argdict(args): r = dict() rom_file = getattr(args, "integrated_rom_file", None)