diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 2e8710b3e..790c69fe2 100644 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -2,7 +2,7 @@ import argparse -from migen import * +from litex.gen import * from litex.boards.platforms import de0nano from litex.soc.cores.sdram.settings import IS42S16160 diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 9cef2f1dd..dfb192449 100644 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -2,8 +2,8 @@ import argparse -from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import kc705 from litex.soc.cores.sdram.settings import MT8JTF12864 diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index b9f1f4e23..7fead6956 100644 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -3,8 +3,8 @@ import argparse from fractions import Fraction -from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import minispartan6 from litex.soc.cores.sdram.settings import AS4C16M16 diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 683545d88..713a2269e 100644 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -3,9 +3,9 @@ import argparse import importlib -from migen import * +from litex.gen import * from litex.boards.platforms import sim -from migen.genlib.io import CRG +from litex.gen.genlib.io import CRG from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 2c24cba0f..05b5a1cda 100644 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -3,8 +3,8 @@ import argparse import importlib -from migen import * -from migen.genlib.io import CRG +from litex.gen import * +from litex.gen.genlib.io import CRG from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py index fafb49837..07b6ef76a 100644 --- a/litex/build/altera/common.py +++ b/litex/build/altera/common.py @@ -1,6 +1,6 @@ -from migen.fhdl.module import Module -from migen.fhdl.specials import Instance -from migen.genlib.io import DifferentialInput, DifferentialOutput +from litex.gen.fhdl.module import Module +from litex.gen.fhdl.specials import Instance +from litex.gen.genlib.io import DifferentialInput, DifferentialOutput class AlteraDifferentialInputImpl(Module): diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py index 011bd8053..d5eda886f 100644 --- a/litex/build/altera/quartus.py +++ b/litex/build/altera/quartus.py @@ -4,7 +4,7 @@ import os import subprocess -from migen.fhdl.structure import _Fragment +from litex.gen.fhdl.structure import _Fragment from litex.build.generic_platform import Pins, IOStandard, Misc from litex.build import tools diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py index 0ef51d1e5..f6320acc9 100644 --- a/litex/build/generic_platform.py +++ b/litex/build/generic_platform.py @@ -1,9 +1,9 @@ import os -from migen.fhdl.structure import Signal -from migen.genlib.record import Record -from migen.genlib.io import CRG -from migen.fhdl import verilog, edif +from litex.gen.fhdl.structure import Signal +from litex.gen.genlib.record import Record +from litex.gen.genlib.io import CRG +from litex.gen.fhdl import verilog, edif from litex.build import tools diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py index c25e8b903..52cf28d9a 100644 --- a/litex/build/lattice/common.py +++ b/litex/build/lattice/common.py @@ -1,7 +1,7 @@ -from migen.fhdl.module import Module -from migen.fhdl.specials import Instance -from migen.genlib.io import * -from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen.fhdl.module import Module +from litex.gen.fhdl.specials import Instance +from litex.gen.genlib.io import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer class LatticeAsyncResetSynchronizerImpl(Module): diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py index ac967654e..cd169fdbc 100644 --- a/litex/build/lattice/diamond.py +++ b/litex/build/lattice/diamond.py @@ -6,7 +6,7 @@ import sys import subprocess import shutil -from migen.fhdl.structure import _Fragment +from litex.gen.fhdl.structure import _Fragment from litex.build.generic_platform import * from litex.build import tools diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index ab54984fe..fb8e87102 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -4,7 +4,7 @@ import os import subprocess -from migen.fhdl.structure import _Fragment +from litex.gen.fhdl.structure import _Fragment from litex.build import tools from litex.build.generic_platform import * diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index 3b50b667d..69c153846 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -2,13 +2,13 @@ import os import sys from distutils.version import StrictVersion -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.fhdl.module import Module -from migen.fhdl.specials import SynthesisDirective -from migen.genlib.cdc import * -from migen.genlib.resetsync import AsyncResetSynchronizer -from migen.genlib.io import * +from litex.gen.fhdl.structure import * +from litex.gen.fhdl.specials import Instance +from litex.gen.fhdl.module import Module +from litex.gen.fhdl.specials import SynthesisDirective +from litex.gen.genlib.cdc import * +from litex.gen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen.genlib.io import * from litex.build import tools diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py index e8698e5e9..8efa5d7a1 100644 --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -2,7 +2,7 @@ import os import subprocess import sys -from migen.fhdl.structure import _Fragment +from litex.gen.fhdl.structure import _Fragment from litex.build.generic_platform import * from litex.build import tools from litex.build.xilinx import common diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index 3900fd864..18474d3d2 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -5,7 +5,7 @@ import os import subprocess import sys -from migen.fhdl.structure import _Fragment +from litex.gen.fhdl.structure import _Fragment from litex.build.generic_platform import * from litex.build import tools from litex.build.xilinx import common diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index a0fc3b165..b5bc3f562 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -144,7 +144,8 @@ def _printnode(ns, at, level, node, target_filter=None): elif isinstance(node, Case): if node.cases: r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n" - css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0)) + css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)] + css = sorted(css, key=lambda x: x[0].value) for choice, statements in css: r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n" r += _printnode(ns, at, level + 2, statements, target_filter) @@ -359,7 +360,7 @@ def convert(f, ios=None, name="top", ns.clock_domains = f.clock_domains r.ns = ns - src = "/* Machine-generated using Migen */\n" + src = "/* Machine-generated using LiteX gen*/\n" src += _printheader(f, ios, name, ns, reg_initialization=not asic_syntax) src += _printcomb(f, ns, diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index e4d6e697b..7d590c84b 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -1,6 +1,6 @@ import os -from migen import * +from litex.gen import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index f2036d810..8511fff5f 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -1,6 +1,6 @@ import os -from migen import * +from litex.gen import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/flash/nor_flash_16.py b/litex/soc/cores/flash/nor_flash_16.py index fa6e0c087..3027882a0 100644 --- a/litex/soc/cores/flash/nor_flash_16.py +++ b/litex/soc/cores/flash/nor_flash_16.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/flash/spi_flash.py b/litex/soc/cores/flash/spi_flash.py index 289ef39b2..69b86004b 100644 --- a/litex/soc/cores/flash/spi_flash.py +++ b/litex/soc/cores/flash/spi_flash.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.misc import timeline +from litex.gen import * +from litex.gen.genlib.misc import timeline from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index 89ccd54d3..463e1e20c 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.cdc import MultiReg +from litex.gen import * +from litex.gen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/identifier.py b/litex/soc/cores/identifier.py index c63840b9a..5baedca15 100644 --- a/litex/soc/cores/identifier.py +++ b/litex/soc/cores/identifier.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * class Identifier(Module): diff --git a/litex/soc/cores/liteeth_mini/common.py b/litex/soc/cores/liteeth_mini/common.py index 3f16e91cf..f08227a9f 100644 --- a/litex/soc/cores/liteeth_mini/common.py +++ b/litex/soc/cores/liteeth_mini/common.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.record import * +from litex.gen import * +from litex.gen.genlib.record import * from litex.soc.interconnect.csr import * from litex.soc.interconnect.stream import * diff --git a/litex/soc/cores/liteeth_mini/mac/__init__.py b/litex/soc/cores/liteeth_mini/mac/__init__.py index 1338e6373..3bc6d3c8b 100644 --- a/litex/soc/cores/liteeth_mini/mac/__init__.py +++ b/litex/soc/cores/liteeth_mini/mac/__init__.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * from litex.soc.cores.liteeth_mini.common import * diff --git a/litex/soc/cores/liteeth_mini/mac/core/__init__.py b/litex/soc/cores/liteeth_mini/mac/core/__init__.py index 82241f5d2..c3bf519bd 100644 --- a/litex/soc/cores/liteeth_mini/mac/core/__init__.py +++ b/litex/soc/cores/liteeth_mini/mac/core/__init__.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * from litex.soc.cores.liteeth_mini.common import * diff --git a/litex/soc/cores/liteeth_mini/mac/core/crc.py b/litex/soc/cores/liteeth_mini/mac/core/crc.py index 05a7f00e7..3e599466c 100644 --- a/litex/soc/cores/liteeth_mini/mac/core/crc.py +++ b/litex/soc/cores/liteeth_mini/mac/core/crc.py @@ -2,8 +2,8 @@ from collections import OrderedDict from functools import reduce from operator import xor -from migen import * -from migen.genlib.misc import chooser +from litex.gen import * +from litex.gen.genlib.misc import chooser from litex.soc.interconnect.stream import * diff --git a/litex/soc/cores/liteeth_mini/mac/core/gap.py b/litex/soc/cores/liteeth_mini/mac/core/gap.py index 30c35660f..72406763f 100644 --- a/litex/soc/cores/liteeth_mini/mac/core/gap.py +++ b/litex/soc/cores/liteeth_mini/mac/core/gap.py @@ -1,7 +1,7 @@ import math -from migen import * -from migen.genlib.fsm import * +from litex.gen import * +from litex.gen.genlib.fsm import * from litex.soc.interconnect.stream import Sink, Source from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap diff --git a/litex/soc/cores/liteeth_mini/mac/core/last_be.py b/litex/soc/cores/liteeth_mini/mac/core/last_be.py index 255ed7c7f..da154c6af 100644 --- a/litex/soc/cores/liteeth_mini/mac/core/last_be.py +++ b/litex/soc/cores/liteeth_mini/mac/core/last_be.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.stream import * from litex.soc.cores.liteeth_mini.common import eth_phy_description diff --git a/litex/soc/cores/liteeth_mini/mac/core/padding.py b/litex/soc/cores/liteeth_mini/mac/core/padding.py index 1bdba9094..8261a9473 100644 --- a/litex/soc/cores/liteeth_mini/mac/core/padding.py +++ b/litex/soc/cores/liteeth_mini/mac/core/padding.py @@ -1,6 +1,6 @@ import math -from migen import * +from litex.gen import * from litex.soc.interconnect.stream import * from litex.soc.cores.liteeth_mini.common import eth_phy_description diff --git a/litex/soc/cores/liteeth_mini/mac/core/preamble.py b/litex/soc/cores/liteeth_mini/mac/core/preamble.py index 0da287884..53ea85af7 100644 --- a/litex/soc/cores/liteeth_mini/mac/core/preamble.py +++ b/litex/soc/cores/liteeth_mini/mac/core/preamble.py @@ -1,7 +1,7 @@ -from migen import * -from migen.genlib.fsm import * -from migen.genlib.misc import chooser -from migen.genlib.record import Record +from litex.gen import * +from litex.gen.genlib.fsm import * +from litex.gen.genlib.misc import chooser +from litex.gen.genlib.record import Record from litex.soc.interconnect.stream import * from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_preamble diff --git a/litex/soc/cores/liteeth_mini/mac/frontend/wishbone.py b/litex/soc/cores/liteeth_mini/mac/frontend/wishbone.py index 72b99df08..3d42d99c7 100644 --- a/litex/soc/cores/liteeth_mini/mac/frontend/wishbone.py +++ b/litex/soc/cores/liteeth_mini/mac/frontend/wishbone.py @@ -1,5 +1,5 @@ -from migen import * -from migen.fhdl.simplify import FullMemoryWE +from litex.gen import * +from litex.gen.fhdl.simplify import FullMemoryWE from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/liteeth_mini/phy/gmii.py b/litex/soc/cores/liteeth_mini/phy/gmii.py index e73cc3413..d2c59cdca 100644 --- a/litex/soc/cores/liteeth_mini/phy/gmii.py +++ b/litex/soc/cores/liteeth_mini/phy/gmii.py @@ -1,6 +1,6 @@ -from migen import * -from migen.genlib.io import DDROutput -from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen import * +from litex.gen.genlib.io import DDROutput +from litex.gen.genlib.resetsync import AsyncResetSynchronizer from litex.soc.cores.liteeth_mini.common import * diff --git a/litex/soc/cores/liteeth_mini/phy/gmii_mii.py b/litex/soc/cores/liteeth_mini/phy/gmii_mii.py index 4ea06eeca..3d8149867 100644 --- a/litex/soc/cores/liteeth_mini/phy/gmii_mii.py +++ b/litex/soc/cores/liteeth_mini/phy/gmii_mii.py @@ -1,6 +1,6 @@ -from migen import * -from migen.genlib.io import DDROutput -from migen.genlib.cdc import PulseSynchronizer +from litex.gen import * +from litex.gen.genlib.io import DDROutput +from litex.gen.genlib.cdc import PulseSynchronizer from litex.soc.interconnect.stream import * from litex.soc.cores.liteeth_mini.common import * diff --git a/litex/soc/cores/liteeth_mini/phy/loopback.py b/litex/soc/cores/liteeth_mini/phy/loopback.py index fd7583c6a..161b35b15 100644 --- a/litex/soc/cores/liteeth_mini/phy/loopback.py +++ b/litex/soc/cores/liteeth_mini/phy/loopback.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * from litex.soc.interconnect.stream import * diff --git a/litex/soc/cores/liteeth_mini/phy/mii.py b/litex/soc/cores/liteeth_mini/phy/mii.py index 5072091ad..f206b2a80 100644 --- a/litex/soc/cores/liteeth_mini/phy/mii.py +++ b/litex/soc/cores/liteeth_mini/phy/mii.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * from litex.soc.interconnect.stream import * diff --git a/litex/soc/cores/liteeth_mini/phy/s6rgmii.py b/litex/soc/cores/liteeth_mini/phy/s6rgmii.py index b2b2876a1..62e115788 100644 --- a/litex/soc/cores/liteeth_mini/phy/s6rgmii.py +++ b/litex/soc/cores/liteeth_mini/phy/s6rgmii.py @@ -1,9 +1,9 @@ # RGMII PHY for Spartan-6 -from migen import * -from migen.genlib.io import DDROutput -from migen.genlib.misc import WaitTimer -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.genlib.io import DDROutput +from litex.gen.genlib.misc import WaitTimer +from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect.stream import * from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/sdram/dfii.py b/litex/soc/cores/sdram/dfii.py index e0b58047d..6051dddae 100644 --- a/litex/soc/cores/sdram/dfii.py +++ b/litex/soc/cores/sdram/dfii.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect import dfi from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/sdram/lasmicon/bankmachine.py b/litex/soc/cores/sdram/lasmicon/bankmachine.py index 06fc10da9..7a9b26c87 100644 --- a/litex/soc/cores/sdram/lasmicon/bankmachine.py +++ b/litex/soc/cores/sdram/lasmicon/bankmachine.py @@ -1,7 +1,7 @@ -from migen import * -from migen.genlib.roundrobin import * -from migen.genlib.fsm import FSM, NextState -from migen.genlib.fifo import SyncFIFO +from litex.gen import * +from litex.gen.genlib.roundrobin import * +from litex.gen.genlib.fsm import FSM, NextState +from litex.gen.genlib.fifo import SyncFIFO from litex.soc.cores.sdram.lasmicon.multiplexer import * diff --git a/litex/soc/cores/sdram/lasmicon/core.py b/litex/soc/cores/sdram/lasmicon/core.py index dc358b60b..a6625015f 100644 --- a/litex/soc/cores/sdram/lasmicon/core.py +++ b/litex/soc/cores/sdram/lasmicon/core.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect import dfi, lasmi_bus from litex.soc.cores.sdram.lasmicon.refresher import * diff --git a/litex/soc/cores/sdram/lasmicon/multiplexer.py b/litex/soc/cores/sdram/lasmicon/multiplexer.py index 66987e07c..af118c502 100644 --- a/litex/soc/cores/sdram/lasmicon/multiplexer.py +++ b/litex/soc/cores/sdram/lasmicon/multiplexer.py @@ -1,9 +1,9 @@ from functools import reduce from operator import or_, and_ -from migen import * -from migen.genlib.roundrobin import * -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.genlib.roundrobin import * +from litex.gen.genlib.fsm import FSM, NextState from litex.soc.cores.sdram.lasmicon.perf import Bandwidth from litex.soc.interconnect.csr import AutoCSR diff --git a/litex/soc/cores/sdram/lasmicon/perf.py b/litex/soc/cores/sdram/lasmicon/perf.py index 1e86285e1..dbd62d3a6 100644 --- a/litex/soc/cores/sdram/lasmicon/perf.py +++ b/litex/soc/cores/sdram/lasmicon/perf.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/sdram/lasmicon/refresher.py b/litex/soc/cores/sdram/lasmicon/refresher.py index 5de9b35d9..e4c5da92c 100644 --- a/litex/soc/cores/sdram/lasmicon/refresher.py +++ b/litex/soc/cores/sdram/lasmicon/refresher.py @@ -1,6 +1,6 @@ -from migen import * -from migen.genlib.misc import timeline -from migen.genlib.fsm import FSM +from litex.gen import * +from litex.gen.genlib.misc import timeline +from litex.gen.genlib.fsm import FSM from litex.soc.cores.sdram.lasmicon.multiplexer import * diff --git a/litex/soc/cores/sdram/minicon/core.py b/litex/soc/cores/sdram/minicon/core.py index cc5800d08..13600b7fc 100644 --- a/litex/soc/cores/sdram/minicon/core.py +++ b/litex/soc/cores/sdram/minicon/core.py @@ -1,9 +1,9 @@ from functools import reduce from operator import or_ -from migen import * -from migen.genlib.fsm import FSM, NextState -from migen.genlib.misc import WaitTimer +from litex.gen import * +from litex.gen.genlib.fsm import FSM, NextState +from litex.gen.genlib.misc import WaitTimer from litex.soc.interconnect import dfi as dfibus from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/sdram/model.py b/litex/soc/cores/sdram/model.py index 7f9a92910..a8792250a 100644 --- a/litex/soc/cores/sdram/model.py +++ b/litex/soc/cores/sdram/model.py @@ -6,8 +6,8 @@ # TODO: # - add $display support to LiteX gen and manage timing violations? -from migen import * -from migen.fhdl.specials import * +from litex.gen import * +from litex.gen.fhdl.specials import * from litex.soc.interconnect.dfi import * from functools import reduce diff --git a/litex/soc/cores/sdram/phy/gensdrphy.py b/litex/soc/cores/sdram/phy/gensdrphy.py index 799be7e04..303faeb0b 100644 --- a/litex/soc/cores/sdram/phy/gensdrphy.py +++ b/litex/soc/cores/sdram/phy/gensdrphy.py @@ -21,9 +21,9 @@ # This PHY only supports CAS Latency 2. # -from migen import * -from migen.genlib.record import * -from migen.fhdl.specials import Tristate +from litex.gen import * +from litex.gen.genlib.record import * +from litex.gen.fhdl.specials import Tristate from litex.soc.interconnect.dfi import * from litex.soc.cores.sdram import settings as sdram_settings diff --git a/litex/soc/cores/sdram/phy/k7ddrphy.py b/litex/soc/cores/sdram/phy/k7ddrphy.py index 7bd4df85c..385bbc9bb 100644 --- a/litex/soc/cores/sdram/phy/k7ddrphy.py +++ b/litex/soc/cores/sdram/phy/k7ddrphy.py @@ -1,6 +1,6 @@ # tCK=5ns CL=7 CWL=6 -from migen import * +from litex.gen import * from litex.soc.interconnect.dfi import * from litex.soc.interconnect.csr import * diff --git a/litex/soc/cores/sdram/phy/s6ddrphy.py b/litex/soc/cores/sdram/phy/s6ddrphy.py index 4781736e1..dfd3e0a2c 100644 --- a/litex/soc/cores/sdram/phy/s6ddrphy.py +++ b/litex/soc/cores/sdram/phy/s6ddrphy.py @@ -19,8 +19,8 @@ from functools import reduce from operator import or_ -from migen import * -from migen.genlib.record import * +from litex.gen import * +from litex.gen.genlib.record import * from litex.soc.interconnect.dfi import * from litex.soc.cores.sdram import settings as sdram_settings diff --git a/litex/soc/cores/sdram/settings.py b/litex/soc/cores/sdram/settings.py index ce575a4ab..0e99ac12c 100644 --- a/litex/soc/cores/sdram/settings.py +++ b/litex/soc/cores/sdram/settings.py @@ -1,7 +1,7 @@ from math import ceil from collections import namedtuple -from migen import * +from litex.gen import * PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency") diff --git a/litex/soc/cores/sdram/tester.py b/litex/soc/cores/sdram/tester.py index 6036bff9b..28b0318e4 100644 --- a/litex/soc/cores/sdram/tester.py +++ b/litex/soc/cores/sdram/tester.py @@ -1,7 +1,7 @@ from functools import reduce from operator import xor -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * from litex.soc.interconnect import dma_lasmi @@ -114,8 +114,8 @@ class _LFSRTB(Module): print("{0:032x}".format(selfp.dut.o)) if __name__ == "__main__": - from migen.fhdl import verilog - from migen.sim.generic import run_simulation + from litex.gen.fhdl import verilog + from litex.gen.sim.generic import run_simulation lfsr = LFSR(3, 4, [3, 2]) print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o})) diff --git a/litex/soc/cores/spi/core.py b/litex/soc/cores/spi/core.py index 1658d949c..56db5020d 100644 --- a/litex/soc/cores/spi/core.py +++ b/litex/soc/cores/spi/core.py @@ -1,6 +1,6 @@ -from migen import * -from migen.bank.description import * -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.bank.description import * +from litex.gen.genlib.fsm import FSM, NextState class SPIMaster(Module, AutoCSR): diff --git a/litex/soc/cores/spi/test.py b/litex/soc/cores/spi/test.py index 065600833..bed69b144 100644 --- a/litex/soc/cores/spi/test.py +++ b/litex/soc/cores/spi/test.py @@ -1,6 +1,6 @@ -from migen import * -from migen.genlib.record import * -from migen.sim.generic import run_simulation +from litex.gen import * +from litex.gen.genlib.record import * +from litex.gen.sim.generic import run_simulation from litex.soc.com.spi import SPIMaster diff --git a/litex/soc/cores/timer.py b/litex/soc/cores/timer.py index fdfefde2d..d98a85e95 100644 --- a/litex/soc/cores/timer.py +++ b/litex/soc/cores/timer.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * diff --git a/litex/soc/cores/uart/bridge.py b/litex/soc/cores/uart/bridge.py index 07ef3bda8..6f47779ab 100644 --- a/litex/soc/cores/uart/bridge.py +++ b/litex/soc/cores/uart/bridge.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge from litex.soc.cores.uart.core import RS232PHY diff --git a/litex/soc/cores/uart/core.py b/litex/soc/cores/uart/core.py index ee6075cc0..d394f5aa7 100644 --- a/litex/soc/cores/uart/core.py +++ b/litex/soc/cores/uart/core.py @@ -1,6 +1,6 @@ -from migen import * -from migen.genlib.record import Record -from migen.genlib.cdc import MultiReg +from litex.gen import * +from litex.gen.genlib.record import Record +from litex.gen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py index 636e305e8..4648b1b87 100644 --- a/litex/soc/integration/cpu_interface.py +++ b/litex/soc/integration/cpu_interface.py @@ -1,4 +1,4 @@ -from migen import * +from litex.gen import * from litex.soc.interconnect.csr import CSRStatus diff --git a/litex/soc/integration/sdram_init.py b/litex/soc/integration/sdram_init.py index 8ca1db005..1f73c1ecb 100644 --- a/litex/soc/integration/sdram_init.py +++ b/litex/soc/integration/sdram_init.py @@ -1,4 +1,4 @@ -from migen import log2_int +from litex.gen import log2_int def get_sdram_phy_header(sdram_phy_settings): diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 567c0a7c8..21dd93737 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -1,6 +1,6 @@ from operator import itemgetter -from migen import * +from litex.gen import * from litex.soc.cores import identifier, timer, uart from litex.soc.cores.cpu import lm32, mor1kx diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 8967657f8..3c3a3e836 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.record import * +from litex.gen import * +from litex.gen.genlib.record import * from litex.soc.interconnect import wishbone, wishbone2lasmi, lasmi_bus from litex.soc.interconnect.csr import AutoCSR @@ -84,7 +84,7 @@ class SoCSDRAM(SoCCore): # Remove this workaround when fixed by Xilinx. from litex.build.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): - from migen.fhdl.simplify import FullMemoryWE + from litex.gen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache) else: self.submodules.l2_cache = l2_cache @@ -97,7 +97,7 @@ class SoCSDRAM(SoCCore): # Remove this workaround when fixed by Xilinx. from litex.build.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): - from migen.fhdl.simplify import FullMemoryWE + from litex.gen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache) else: self.submodules.l2_cache = l2_cache diff --git a/litex/soc/interconnect/csr.py b/litex/soc/interconnect/csr.py index 8183b2e01..c4458cdeb 100644 --- a/litex/soc/interconnect/csr.py +++ b/litex/soc/interconnect/csr.py @@ -1,6 +1,6 @@ -from migen import * -from migen.util.misc import xdir -from migen.fhdl.tracer import get_obj_var_name +from litex.gen import * +from litex.gen.util.misc import xdir +from litex.gen.fhdl.tracer import get_obj_var_name class _CSRBase(DUID): diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index 5e21d8dca..128199275 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -1,7 +1,7 @@ -from migen import * -from migen.genlib.record import * -from migen.genlib.misc import chooser -from migen.util.misc import xdir +from litex.gen import * +from litex.gen.genlib.record import * +from litex.gen.genlib.misc import chooser +from litex.gen.util.misc import xdir from litex.soc.interconnect import csr from litex.soc.interconnect.csr import CSRStorage diff --git a/litex/soc/interconnect/csr_eventmanager.py b/litex/soc/interconnect/csr_eventmanager.py index 56258ff7d..12b85a0a9 100644 --- a/litex/soc/interconnect/csr_eventmanager.py +++ b/litex/soc/interconnect/csr_eventmanager.py @@ -1,8 +1,8 @@ from functools import reduce from operator import or_ -from migen import * -from migen.util.misc import xdir +from litex.gen import * +from litex.gen.util.misc import xdir from litex.soc.interconnect.csr import * diff --git a/litex/soc/interconnect/dfi.py b/litex/soc/interconnect/dfi.py index aae56b0d3..25812122e 100644 --- a/litex/soc/interconnect/dfi.py +++ b/litex/soc/interconnect/dfi.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.record import * +from litex.gen import * +from litex.gen.genlib.record import * def phase_cmd_description(addressbits, bankbits): diff --git a/litex/soc/interconnect/dma_lasmi.py b/litex/soc/interconnect/dma_lasmi.py index ce3937bc7..1d1e99984 100644 --- a/litex/soc/interconnect/dma_lasmi.py +++ b/litex/soc/interconnect/dma_lasmi.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.fifo import SyncFIFO +from litex.gen import * +from litex.gen.genlib.fifo import SyncFIFO class Reader(Module): diff --git a/litex/soc/interconnect/lasmi_bus.py b/litex/soc/interconnect/lasmi_bus.py index c8d2ded26..841b72b16 100644 --- a/litex/soc/interconnect/lasmi_bus.py +++ b/litex/soc/interconnect/lasmi_bus.py @@ -1,9 +1,9 @@ from functools import reduce from operator import or_ -from migen import * -from migen.genlib import roundrobin -from migen.genlib.record import * +from litex.gen import * +from litex.gen.genlib import roundrobin +from litex.gen.genlib.record import * class Interface(Record): diff --git a/litex/soc/interconnect/packet.py b/litex/soc/interconnect/packet.py index 569f3114f..bac7c9150 100644 --- a/litex/soc/interconnect/packet.py +++ b/litex/soc/interconnect/packet.py @@ -1,7 +1,7 @@ -from migen import * -from migen.genlib.roundrobin import * -from migen.genlib.record import * -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.genlib.roundrobin import * +from litex.gen.genlib.record import * +from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect.stream import * diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 0647af94b..cceb8c422 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -1,6 +1,6 @@ -from migen import * -from migen.genlib.record import * -from migen.genlib import fifo +from litex.gen import * +from litex.gen.genlib.record import * +from litex.gen.genlib import fifo def _make_m2s(layout): @@ -159,7 +159,7 @@ class Demultiplexer(Module): # XXX from copy import copy -from migen.util.misc import xdir +from litex.gen.util.misc import xdir def pack_layout(l, n): return [("chunk"+str(i), l) for i in range(n)] diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 5b51431a2..c10cda4ee 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -1,11 +1,11 @@ from functools import reduce from operator import or_ -from migen import * -from migen.genlib import roundrobin -from migen.genlib.record import * -from migen.genlib.misc import split, displacer, chooser -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.genlib import roundrobin +from litex.gen.genlib.record import * +from litex.gen.genlib.misc import split, displacer, chooser +from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect import csr diff --git a/litex/soc/interconnect/wishbone2csr.py b/litex/soc/interconnect/wishbone2csr.py index 1d7171a31..25efdc6fd 100644 --- a/litex/soc/interconnect/wishbone2csr.py +++ b/litex/soc/interconnect/wishbone2csr.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.misc import timeline +from litex.gen import * +from litex.gen.genlib.misc import timeline from litex.soc.interconnect import csr_bus, wishbone diff --git a/litex/soc/interconnect/wishbone2lasmi.py b/litex/soc/interconnect/wishbone2lasmi.py index 9c95689c4..bd139afa3 100644 --- a/litex/soc/interconnect/wishbone2lasmi.py +++ b/litex/soc/interconnect/wishbone2lasmi.py @@ -1,5 +1,5 @@ -from migen import * -from migen.genlib.fsm import FSM, NextState +from litex.gen import * +from litex.gen.genlib.fsm import FSM, NextState class WB2LASMI(Module): diff --git a/litex/soc/interconnect/wishbonebridge.py b/litex/soc/interconnect/wishbonebridge.py index a664fd1b3..6137beca0 100644 --- a/litex/soc/interconnect/wishbonebridge.py +++ b/litex/soc/interconnect/wishbonebridge.py @@ -1,8 +1,8 @@ -from migen import * +from litex.gen import * -from migen.genlib.misc import chooser, WaitTimer -from migen.genlib.record import Record -from migen.genlib.fsm import FSM, NextState +from litex.gen.genlib.misc import chooser, WaitTimer +from litex.gen.genlib.record import Record +from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect import wishbone from litex.soc.interconnect.stream import Sink, Source