From fca0b968e7e3749e78625a7ccf48fa53dde07d9a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 24 Nov 2013 19:50:17 +0100 Subject: [PATCH] generate linker memory map, move all generated files into the same folder --- .gitignore | 4 ++-- make.py | 6 ++++-- misoclib/gensoc/__init__.py | 16 ++++++++++++---- misoclib/gensoc/cpuif.py | 9 ++++++++- misoclib/s6ddrphy/initsequence.py | 4 ++-- software/bios/boot.c | 2 +- software/bios/isr.c | 2 +- software/bios/linker.ld | 5 +---- software/bios/main.c | 2 +- software/bios/sdram.c | 4 ++-- software/common.mak | 2 +- software/include/generated/.keep_me | 0 software/libbase/id.c | 2 +- software/libbase/linker-sdram.ld | 4 +--- software/libbase/system.c | 2 +- software/libbase/time.c | 2 +- software/libbase/uart.c | 2 +- software/libnet/microudp.c | 2 +- software/memtest/isr.c | 2 +- software/memtest/main.c | 2 +- software/videomixer/ci.c | 2 +- software/videomixer/dvisamplerX.c | 2 +- software/videomixer/isr.c | 2 +- software/videomixer/main.c | 2 +- software/videomixer/pll.c | 2 +- software/videomixer/processor.c | 2 +- targets/mlabs_video.py | 1 + 27 files changed, 50 insertions(+), 37 deletions(-) create mode 100644 software/include/generated/.keep_me diff --git a/.gitignore b/.gitignore index cea03fad1..45c29b2cd 100644 --- a/.gitignore +++ b/.gitignore @@ -9,8 +9,8 @@ build/* tools/flterm tools/mkmscimg tools/byteswap -software/include/hw/csr.h -software/include/hw/sdram_phy.h +software/include/generated/*.h +software/include/generated/*.ld software/videomixer/dvisampler0.c software/videomixer/dvisampler0.h software/videomixer/dvisampler1.c diff --git a/make.py b/make.py index 1103173a6..fea284f3d 100755 --- a/make.py +++ b/make.py @@ -65,10 +65,12 @@ def main(): */ """.format(args.platform, args.target, top_class.__name__) + linker_header = cpuif.get_linker_regions(soc.cpu_memory_regions) + write_to_file("software/include/generated/regions.ld", boilerplate + linker_header) csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map) - write_to_file("software/include/hw/csr.h", boilerplate + csr_header) + write_to_file("software/include/generated/csr.h", boilerplate + csr_header) sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy) - write_to_file("software/include/hw/sdram_phy.h", boilerplate + sdram_phy_header) + write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header) if args.csr_csv: csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray) write_to_file(args.csr_csv, csr_csv) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 71fe7c6d7..c65ea8d0b 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -29,13 +29,14 @@ class GenSoC(Module): "m1": 0x4D31 }) - def __init__(self, platform, clk_freq, sram_size, l2_size=0): + def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size=0): self.clk_freq = clk_freq self.sram_size = sram_size self.l2_size = l2_size + self.cpu_memory_regions = [] # Wishbone - self.submodules.cpu = lm32.LM32() + self.submodules.cpu = lm32.LM32() # TODO: cpu_reset_address self.submodules.sram = wishbone.SRAM(sram_size) self.submodules.wishbone2csr = wishbone2csr.WB2CSR() @@ -47,6 +48,8 @@ class GenSoC(Module): (lambda a: a[26:29] == 1, self.sram.bus), (lambda a: a[27:29] == 3, self.wishbone2csr.wishbone) ] + self.add_cpu_memory_region("rom", cpu_reset_address, 0x8000) # 32KB for BIOS + self.add_cpu_memory_region("sram", 0x10000000, sram_size) # CSR self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200) @@ -74,6 +77,9 @@ class GenSoC(Module): raise FinalizeError self._wb_slaves.append((address_decoder, interface)) + def add_cpu_memory_region(self, name, origin, length): + self.cpu_memory_regions.append((name, origin, length)) + def do_finalize(self): # Wishbone self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, @@ -104,8 +110,8 @@ class SDRAMSoC(GenSoC): } csr_map.update(GenSoC.csr_map) - def __init__(self, platform, clk_freq, sram_size, l2_size, with_memtest): - GenSoC.__init__(self, platform, clk_freq, sram_size, l2_size) + def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_memtest): + GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size) self.with_memtest = with_memtest self._sdram_modules_created = False @@ -132,6 +138,8 @@ class SDRAMSoC(GenSoC): # Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000) self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()) self.add_wb_slave(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone) + self.add_cpu_memory_region("sdram", 0x40000000, + 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8) def do_finalize(self): if not self._sdram_modules_created: diff --git a/misoclib/gensoc/cpuif.py b/misoclib/gensoc/cpuif.py index 0dcdfc16d..9c40b6b9a 100644 --- a/misoclib/gensoc/cpuif.py +++ b/misoclib/gensoc/cpuif.py @@ -1,5 +1,12 @@ from migen.bank.description import CSRStatus +def get_linker_regions(regions): + r = "MEMORY {\n" + for name, origin, length in regions: + r += "\t{} : ORIGIN = 0x{:08x}, LENGTH = 0x{:08x}\n".format(name, origin, length) + r += "}\n" + return r + def _get_rw_functions(reg_name, reg_base, size, read_only): r = "" @@ -39,7 +46,7 @@ def _get_rw_functions(reg_name, reg_base, size, read_only): return r def get_csr_header(csr_base, bank_array, interrupt_map): - r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include \n" + r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include \n" for name, csrs, mapaddr, rmap in bank_array.banks: r += "\n/* "+name+" */\n" reg_base = csr_base + 0x800*mapaddr diff --git a/misoclib/s6ddrphy/initsequence.py b/misoclib/s6ddrphy/initsequence.py index 3c4c65bf3..cf76d4e97 100644 --- a/misoclib/s6ddrphy/initsequence.py +++ b/misoclib/s6ddrphy/initsequence.py @@ -4,8 +4,8 @@ def get_sdram_phy_header(sdram_phy): if sdram_phy.phy_settings.memtype not in ["SDR", "DDR", "LPDDR", "DDR2"]: raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2") - r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n" - r += "#include \n#include \n#include \n\n" + r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" + r += "#include \n#include \n#include \n\n" r += "static void cdelay(int i);\n" diff --git a/software/bios/boot.c b/software/bios/boot.c index 9d9b33632..93ae18cbe 100644 --- a/software/bios/boot.c +++ b/software/bios/boot.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include diff --git a/software/bios/isr.c b/software/bios/isr.c index 36c4c7e07..c49d31d8d 100644 --- a/software/bios/isr.c +++ b/software/bios/isr.c @@ -1,4 +1,4 @@ -#include +#include #include #include diff --git a/software/bios/linker.ld b/software/bios/linker.ld index b21c1e363..302f7e023 100644 --- a/software/bios/linker.ld +++ b/software/bios/linker.ld @@ -3,10 +3,7 @@ ENTRY(_start) __DYNAMIC = 0; -MEMORY { - rom : ORIGIN = 0x00180000, LENGTH = 0x20000 /* 128K */ - sram : ORIGIN = 0x10000000, LENGTH = 0x01000 /* 4K */ -} +INCLUDE generated/regions.ld SECTIONS { diff --git a/software/bios/main.c b/software/bios/main.c index 091b2d919..9c4d878d3 100644 --- a/software/bios/main.c +++ b/software/bios/main.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include diff --git a/software/bios/sdram.c b/software/bios/sdram.c index 8fef0410a..3a4fed44b 100644 --- a/software/bios/sdram.c +++ b/software/bios/sdram.c @@ -1,8 +1,8 @@ #include #include -#include -#include +#include +#include #include #include diff --git a/software/common.mak b/software/common.mak index 7320685e9..c69f2a7f9 100644 --- a/software/common.mak +++ b/software/common.mak @@ -45,7 +45,7 @@ COMMONFLAGS = -Os -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -ms -Wall -fno-builtin -nostdinc -DGIT_ID=$(GIT_ID) $(INCLUDES) CFLAGS = $(COMMONFLAGS) -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes CXXFLAGS = $(COMMONFLAGS) -fno-exceptions -ffreestanding -LDFLAGS = -nostdlib -nodefaultlibs +LDFLAGS = -nostdlib -nodefaultlibs -L$(MSCDIR)/software/include # compile and generate dependencies, based on # http://scottmcpeak.com/autodepend/autodepend.html diff --git a/software/include/generated/.keep_me b/software/include/generated/.keep_me new file mode 100644 index 000000000..e69de29bb diff --git a/software/libbase/id.c b/software/libbase/id.c index a0f92f534..254aa55cc 100644 --- a/software/libbase/id.c +++ b/software/libbase/id.c @@ -1,4 +1,4 @@ -#include +#include #include #include #include diff --git a/software/libbase/linker-sdram.ld b/software/libbase/linker-sdram.ld index fd17edbfd..16cb35e2a 100644 --- a/software/libbase/linker-sdram.ld +++ b/software/libbase/linker-sdram.ld @@ -3,9 +3,7 @@ ENTRY(_start) __DYNAMIC = 0; -MEMORY { - sdram : ORIGIN = 0x40000000, LENGTH = 0x08000000 /* 128M */ -} +INCLUDE generated/regions.ld SECTIONS { diff --git a/software/libbase/system.c b/software/libbase/system.c index fcb585d97..7159e3799 100644 --- a/software/libbase/system.c +++ b/software/libbase/system.c @@ -3,7 +3,7 @@ #include #include -#include +#include void flush_cpu_icache(void) { diff --git a/software/libbase/time.c b/software/libbase/time.c index c809dfd54..4bf95479a 100644 --- a/software/libbase/time.c +++ b/software/libbase/time.c @@ -1,4 +1,4 @@ -#include +#include #include void time_init(void) diff --git a/software/libbase/uart.c b/software/libbase/uart.c index 5b88569bf..13dfe3b1f 100644 --- a/software/libbase/uart.c +++ b/software/libbase/uart.c @@ -1,6 +1,6 @@ #include #include -#include +#include #include /* diff --git a/software/libnet/microudp.c b/software/libnet/microudp.c index d499d6392..09e4c40e5 100644 --- a/software/libnet/microudp.c +++ b/software/libnet/microudp.c @@ -1,7 +1,7 @@ #include #include #include -#include +#include #include #include diff --git a/software/memtest/isr.c b/software/memtest/isr.c index 36c4c7e07..c49d31d8d 100644 --- a/software/memtest/isr.c +++ b/software/memtest/isr.c @@ -1,4 +1,4 @@ -#include +#include #include #include diff --git a/software/memtest/main.c b/software/memtest/main.c index 603e50a25..67143b843 100644 --- a/software/memtest/main.c +++ b/software/memtest/main.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/software/videomixer/ci.c b/software/videomixer/ci.c index f6f1110a6..6b0f43044 100644 --- a/software/videomixer/ci.c +++ b/software/videomixer/ci.c @@ -1,7 +1,7 @@ #include #include -#include +#include #include "dvisampler0.h" #include "dvisampler1.h" diff --git a/software/videomixer/dvisamplerX.c b/software/videomixer/dvisamplerX.c index 088519c70..6ba69232c 100644 --- a/software/videomixer/dvisamplerX.c +++ b/software/videomixer/dvisamplerX.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include "dvisamplerX.h" diff --git a/software/videomixer/isr.c b/software/videomixer/isr.c index aa1139f80..db878a391 100644 --- a/software/videomixer/isr.c +++ b/software/videomixer/isr.c @@ -1,4 +1,4 @@ -#include +#include #include #include diff --git a/software/videomixer/main.c b/software/videomixer/main.c index 998f7f82d..544d1837e 100644 --- a/software/videomixer/main.c +++ b/software/videomixer/main.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/software/videomixer/pll.c b/software/videomixer/pll.c index 1a8689e4a..843a02762 100644 --- a/software/videomixer/pll.c +++ b/software/videomixer/pll.c @@ -1,5 +1,5 @@ #include -#include +#include #include "pll.h" diff --git a/software/videomixer/processor.c b/software/videomixer/processor.c index d5580d1cc..07e73a383 100644 --- a/software/videomixer/processor.c +++ b/software/videomixer/processor.c @@ -1,7 +1,7 @@ #include #include -#include +#include #include #include "dvisampler0.h" diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 580bcdba5..43491c7e6 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -45,6 +45,7 @@ class MiniSoC(SDRAMSoC): def __init__(self, platform, with_memtest=False): SDRAMSoC.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, + cpu_reset_address=0x00180000, sram_size=4096, l2_size=8192, with_memtest=with_memtest)