From fd354c575982ec0b5ebf0f5120d8352897c867fb Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 13 Oct 2021 11:33:43 +0200
Subject: [PATCH] gen/fhdl/memory: Fix dual clock memory pattern (previous
 pattern is no longer supported by Yosys), thanks @gregdavill.

See https://github.com/enjoy-digital/litex/issues/1003.
---
 litex/gen/fhdl/memory.py | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/litex/gen/fhdl/memory.py b/litex/gen/fhdl/memory.py
index 7085f4a92..49a66b25a 100644
--- a/litex/gen/fhdl/memory.py
+++ b/litex/gen/fhdl/memory.py
@@ -21,6 +21,13 @@ def memory_emit_verilog(memory, ns, add_data_file):
     adr_regs = {}
     data_regs = {}
 
+    # https://github.com/enjoy-digital/litex/issues/1003
+    # FIXME: Verify behaviour with the different FPGA toolchains.
+    clocks = [port.clock for port in memory.ports]
+    if clocks.count(clocks[0]) != len(clocks):
+        for port in memory.ports:
+            port.mode = READ_FIRST
+
     for port in memory.ports:
         if not port.async_read:
             if port.mode == WRITE_FIRST: