diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py
index 867a96f4c..2098d0463 100644
--- a/litex/soc/cores/hyperbus.py
+++ b/litex/soc/cores/hyperbus.py
@@ -33,7 +33,7 @@ class HyperRAM(LiteXModule):
     Parameters:
         pads (Record)                  : Interface to the HyperRAM connection pads.
         latency (int, optional)        : Initial latency setting, defaults to 6.
-        latency_mode (str, optional)   : Specifies the latency mode ('fixed' or 'variable'), defaults to 'fixed'.
+        latency_mode (str, optional)   : Specifies the latency mode ('fixed' or 'variable'), defaults to 'variable'.
         sys_clk_freq (float, optional) : System clock frequency in Hz.
         with_csr (bool, optional)      : Enables CSR interface for Latency/Registers configuration, defaults to True.
 
@@ -41,7 +41,7 @@ class HyperRAM(LiteXModule):
         pads (Record)            : Platform pads of HyperRAM.
         bus (wishbone.Interface) : Wishbone Interface.
 """
-    def __init__(self, pads, latency=6, latency_mode="fixed", sys_clk_freq=None, with_csr=True):
+    def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=None, with_csr=True):
         self.pads = pads
         self.bus  = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")