From fe19ee464e091e3ad8a89dee73699907d2947189 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 3 Nov 2023 11:29:48 +0100 Subject: [PATCH] gen/fhdl/memory: Rename memory_emit_verilog to _memory_generate_verilog. --- litex/gen/fhdl/memory.py | 15 ++++++++------- litex/gen/fhdl/verilog.py | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/litex/gen/fhdl/memory.py b/litex/gen/fhdl/memory.py index 545d774a4..56f2847a1 100644 --- a/litex/gen/fhdl/memory.py +++ b/litex/gen/fhdl/memory.py @@ -2,18 +2,19 @@ # This file is part of LiteX (Adapted from Migen for LiteX usage). # # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq -# This file is Copyright (c) 2021 Florent Kermarrec +# This file is Copyright (c) 2021-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause -from migen.fhdl.structure import * -from migen.fhdl.module import * +from migen.fhdl.structure import * +from migen.fhdl.module import * from migen.fhdl.bitcontainer import bits_for -from migen.fhdl.tools import * -from migen.fhdl.verilog import _printexpr as verilog_printexpr -from migen.fhdl.specials import * +from migen.fhdl.tools import * +from migen.fhdl.verilog import _printexpr as verilog_printexpr +from migen.fhdl.specials import * +# LiteX Memory Verilog Generation ------------------------------------------------------------------ -def memory_emit_verilog(name, memory, namespace, add_data_file): +def _memory_generate_verilog(name, memory, namespace, add_data_file): # Helpers. # -------- diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 20d861505..87cf629d8 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -527,8 +527,8 @@ def _generate_specials(name, overrides, specials, namespace, add_data_file, attr r += _generate_attribute(special.attr, attr_translate) # Replace Migen Memory's emit_verilog with LiteX's implementation. if isinstance(special, Memory): - from litex.gen.fhdl.memory import memory_emit_verilog - pr = memory_emit_verilog(name, special, namespace, add_data_file) + from litex.gen.fhdl.memory import _memory_generate_verilog + pr = _memory_generate_verilog(name, special, namespace, add_data_file) else: pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file) if pr is None: