From fe2998a19cbbda9592b212b18ad8141b4dfd4cc2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 15 Oct 2021 15:12:30 +0200 Subject: [PATCH] fhdl/verilog: Remove create_clock_domains (not used in LiteX). --- litex/build/generic_platform.py | 5 +---- litex/gen/fhdl/verilog.py | 17 +++++------------ 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py index 6b0d4c66a..6d95d5ff3 100644 --- a/litex/build/generic_platform.py +++ b/litex/build/generic_platform.py @@ -432,10 +432,7 @@ class GenericPlatform: return named_sc, named_pc def get_verilog(self, fragment, **kwargs): - return verilog.convert( - fragment, - self.constraint_manager.get_io_signals(), - create_clock_domains=False, **kwargs) + return verilog.convert(fragment, self.constraint_manager.get_io_signals(), **kwargs) def get_edif(self, fragment, cell_library, vendor, device, **kwargs): return edif.convert( diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 03e7475d5..44f38e618 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -470,7 +470,6 @@ class DummyAttrTranslate(dict): def convert(f, ios=set(), name="top", special_overrides = dict(), attr_translate = DummyAttrTranslate(), - create_clock_domains = True, blocking_assign = False, regular_comb = True): @@ -486,18 +485,12 @@ def convert(f, ios=set(), name="top", # Try to get Clock Domain. try: f.clock_domains[cd_name] - # If not found, create it if enabled: + # If not found, raise Error. except: - if create_clock_domains: - cd = ClockDomain(cd_name) - f.clock_domains.append(cd) - ios |= {cd.clk, cd.rst} - # Or raise Error. - else: - msg = f"""Unresolved clock domain {cd_name}, availables:\n""" - for f in f.clock_domains: - msg += f"- {f.name}\n" - raise Exception(msg) + msg = f"""Unresolved clock domain {cd_name}, availables:\n""" + for f in f.clock_domains: + msg += f"- {f.name}\n" + raise Exception(msg) # Lower complex slices. f = lower_complex_slices(f)