From feca1c472dcc132b2b8383758b032fcf41125f4f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 10 Nov 2021 12:05:47 +0100
Subject: [PATCH] build/efinix/ifacewriter: Go a bit further in DRAM
integration.
---
litex/build/efinix/ifacewriter.py | 90 ++++++++++++++++++++++---------
1 file changed, 65 insertions(+), 25 deletions(-)
diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py
index f6b737deb..56933a608 100644
--- a/litex/build/efinix/ifacewriter.py
+++ b/litex/build/efinix/ifacewriter.py
@@ -210,14 +210,27 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
cmd += "# ---------- END PLL {} ---------\n\n".format(name)
return cmd
+ def generate_pll_dram(self):
+ return """
+design.create_block("pll_dram", block_type="PLL")
+design.set_property("pll_dram", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
+design.gen_pll_ref_clock("pll_dram", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="clk50", ext_refclk_no="1")
+design.set_property("pll_dram","LOCKED_PIN","pll_dram_locked", block_type="PLL")
+design.set_property("pll_dram","RSTN_PIN","pll_dram_rstn", block_type="PLL")
+design.set_property("pll_dram", {"CLKOUT0_PIN" : "pll_dram_CLKOUT0"}, block_type="PLL")
+design.set_property("pll_dram","CLKOUT0_PHASE","0","PLL")
+calc_result = design.auto_calc_pll_clock("pll_dram", {"CLKOUT0_FREQ": "400.0"})
+"""
+
def generate(self, partnumber):
output = ""
for b in self.blocks:
if b["type"] == "PLL":
output += self.generate_pll(b, partnumber)
+ if b["type"] == "PLL_DRAM":
+ output += self.generate_pll_dram()
if b["type"] == "GPIO":
output += self.generate_gpio(b)
-
return output
def footer(self):
@@ -285,32 +298,59 @@ design.save()"""
)
gen_pin_target0 = et.SubElement(ddr, "efxpt:gen_pin_target0")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wdata", type_name=f"WDATA_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wready", type_name=f"WREADY_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wid", type_name=f"WID_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_bready", type_name=f"BREADY_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rdata", type_name=f"RDATA_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aid", type_name=f"AID_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_bvalid", type_name=f"BVALID_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rlast", type_name=f"RLAST_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_bid", type_name=f"BID_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_asize", type_name=f"ASIZE_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_atype", type_name=f"ATYPE_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aburst", type_name=f"ABURST_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wvalid", type_name=f"WVALID_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wlast", type_name=f"WLAST_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aaddr", type_name=f"AADDR_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rid", type_name=f"RID_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_avalid", type_name=f"AVALID_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rvalid", type_name=f"RVALID_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_alock", type_name=f"ALOCK_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rready", type_name=f"RREADY_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_rresp", type_name=f"RRESP_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_wstrb", type_name=f"WSTRB_0", is_bus="true")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_aready", type_name=f"AREADY_0", is_bus="false")
- et.SubElement(gen_pin_target0, "efxpt:pin", name=f"axi_alen", type_name=f"ALEN_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wdata", type_name=f"WDATA_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wready", type_name=f"WREADY_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wid", type_name=f"WID_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bready", type_name=f"BREADY_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rdata", type_name=f"RDATA_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aid", type_name=f"AID_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bvalid", type_name=f"BVALID_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rlast", type_name=f"RLAST_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bid", type_name=f"BID_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_asize", type_name=f"ASIZE_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_atype", type_name=f"ATYPE_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aburst", type_name=f"ABURST_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wvalid", type_name=f"WVALID_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wlast", type_name=f"WLAST_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aaddr", type_name=f"AADDR_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rid", type_name=f"RID_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_avalid", type_name=f"AVALID_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rvalid", type_name=f"RVALID_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alock", type_name=f"ALOCK_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rready", type_name=f"RREADY_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rresp", type_name=f"RRESP_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wstrb", type_name=f"WSTRB_0", is_bus="true")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aready", type_name=f"AREADY_0", is_bus="false")
+ et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alen", type_name=f"ALEN_0", is_bus="true")
et.SubElement(gen_pin_target0, "efxpt:pin", name="axi_clk", type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false")
+ gen_pin_target1 = et.SubElement(ddr, "efxpt:gen_pin_target1")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wdata", type_name=f"WDATA_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wready", type_name=f"WREADY_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wid", type_name=f"WID_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bready", type_name=f"BREADY_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rdata", type_name=f"RDATA_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aid", type_name=f"AID_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bvalid", type_name=f"BVALID_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rlast", type_name=f"RLAST_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bid", type_name=f"BID_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_asize", type_name=f"ASIZE_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_atype", type_name=f"ATYPE_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aburst", type_name=f"ABURST_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wvalid", type_name=f"WVALID_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wlast", type_name=f"WLAST_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aaddr", type_name=f"AADDR_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rid", type_name=f"RID_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_avalid", type_name=f"AVALID_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rvalid", type_name=f"RVALID_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alock", type_name=f"ALOCK_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rready", type_name=f"RREADY_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rresp", type_name=f"RRESP_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wstrb", type_name=f"WSTRB_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aready", type_name=f"AREADY_1", is_bus="false")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alen", type_name=f"ALEN_1", is_bus="true")
+ et.SubElement(gen_pin_target1, "efxpt:pin", name="axi_clk", type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false")
+
gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config")
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SEQ_RST", is_bus="false")
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SCL_IN", is_bus="false")