From fefc5aae664629788a7082bec623985bce80de75 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Apr 2021 10:40:24 +0200 Subject: [PATCH] cores/video/VideoVGAPHY: Add optional clk support. Some LCDs displays are almost VGA compatible (no DE, active low hsync/vsync) but require the clock. --- litex/soc/cores/video.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py index 405c8c153..c1d9d5230 100644 --- a/litex/soc/cores/video.py +++ b/litex/soc/cores/video.py @@ -667,6 +667,10 @@ class VideoVGAPHY(Module): # Always ack Sink, no backpressure. self.comb += sink.ready.eq(1) + # Drive VGA Clk (Optional). + if hasattr(pads, "clk"): + self.comb += pads.clk.eq(ClockSignal(clock_domain)) + # Drive VGA Conrols. self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))