From ff23960657faccf656f0f4f9d749194dc180e6c4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Apr 2015 17:18:07 +0200 Subject: [PATCH] fhdl/verilog: avoid reg initialization in printheader when reset is not an int. We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one. --- migen/fhdl/verilog.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index c1cfc690e..eac214c60 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -172,7 +172,11 @@ def _printheader(f, ios, name, ns): if sig in wires: r += "wire " + _printsig(ns, sig) + ";\n" else: - r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n" + if isinstance(sig.reset, int): + resetexpr = " = " + _printexpr(ns, sig.reset)[0] + else: + resetexpr = "" + r += "reg " + _printsig(ns, sig) + resetexpr + ";\n" r += "\n" return r