From ff6e7bd6add8f8b25b82ccc0962297d9cc57d6e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 20 Apr 2022 11:01:21 +0200 Subject: [PATCH] cores/uart/Stream2Wishbone: Add asserts on data_width/address_width. --- litex/soc/cores/uart.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index dad878913..5a6d147b9 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -311,6 +311,8 @@ class Stream2Wishbone(Module): self.wishbone = wishbone.Interface(data_width=data_width, adr_width=address_width) # # # + assert data_width in [8, 16, 32] + assert address_width in [8, 16, 32] cmd = Signal(8, reset_less=True) incr = Signal()