From ff72757b870d6ac810cba7fcf8c5400a163e8340 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 29 Oct 2017 10:39:01 -0700 Subject: [PATCH] Bump the IRQ for liteeth based targets. --- litex/boards/targets/arty.py | 2 +- litex/boards/targets/kc705.py | 2 +- litex/boards/targets/nexys_video.py | 2 +- litex/boards/targets/sim.py | 2 +- litex/boards/targets/simple.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 75d58a9b5..64d892f87 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -124,7 +124,7 @@ class MiniSoC(BaseSoC): csr_map.update(BaseSoC.csr_map) interrupt_map = { - "ethmac": 2, + "ethmac": 3, } interrupt_map.update(BaseSoC.interrupt_map) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 37297f330..541d3dea9 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -104,7 +104,7 @@ class MiniSoC(BaseSoC): csr_map.update(BaseSoC.csr_map) interrupt_map = { - "ethmac": 2, + "ethmac": 3, } interrupt_map.update(BaseSoC.interrupt_map) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 75774e945..77b54688b 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -113,7 +113,7 @@ class MiniSoC(BaseSoC): csr_map.update(BaseSoC.csr_map) interrupt_map = { - "ethmac": 2, + "ethmac": 3, } interrupt_map.update(BaseSoC.interrupt_map) diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 1624441fc..04371fd9f 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -68,7 +68,7 @@ class MiniSoC(BaseSoC): csr_map.update(BaseSoC.csr_map) interrupt_map = { - "ethmac": 2, + "ethmac": 3, } interrupt_map.update(BaseSoC.interrupt_map) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 179581b43..88c8afd37 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -30,7 +30,7 @@ class MiniSoC(BaseSoC): csr_map.update(BaseSoC.csr_map) interrupt_map = { - "ethmac": 2, + "ethmac": 3, } interrupt_map.update(BaseSoC.interrupt_map)