From ff7e0fab6a0afa2698db9721502b9c6ea0e74978 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 25 Feb 2019 18:02:04 +0000 Subject: [PATCH] versa_ecp5: Add option to build with Trellis --- litex/boards/targets/versa_ecp5.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 85c0b1cff..e670499eb 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -68,8 +68,8 @@ class BaseSoC(SoCSDRAM): "ddrphy": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, **kwargs): - platform = versa_ecp5.Platform(toolchain="diamond") + def __init__(self, toolchain="diamond", **kwargs): + platform = versa_ecp5.Platform(toolchain=toolchain) sys_clk_freq = int(50e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, @@ -95,11 +95,13 @@ class BaseSoC(SoCSDRAM): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECP5") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", + help='gateware toolchain to use, diamond (default) or trellis') builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build()