From ffb6081720eb1d4254dd774680d5b203e65cd271 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 26 Jun 2015 01:15:34 +0200 Subject: [PATCH] litesata/example_designs: Add missing clock in phy instantiation --- misoclib/mem/litesata/example_designs/targets/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py index d841d4ecd..e15b259a8 100644 --- a/misoclib/mem/litesata/example_designs/targets/core.py +++ b/misoclib/mem/litesata/example_designs/targets/core.py @@ -17,7 +17,7 @@ class Core(Module): self.clk_freq = clk_freq # SATA PHY/Core/Frontend - self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq) + self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq) self.submodules.sata_core = LiteSATACore(self.sata_phy) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)