Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteScope footprint is really small!

LiteScope generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit user's needs! (Data width, storage depth, storage qualifier and so on...)

Liscope can target all FPGAs regardless of the vendor, so you keep your debug methology accross all the FPGA designs you are developing!