import unittest import random from migen import * from litedram.common import * from litedram.frontend.axi import * from litex.gen.sim import * class Burst: def __init__(self, addr, type=BURST_FIXED, len=0, size=0): self.addr = addr self.type = type self.len = len self.size = size def to_beats(self): r = [] for i in range(self.len + 1): if self.type == BURST_INCR: offset = i*2**(self.size) r += [Beat(self.addr + offset)] elif self.type == BURST_WRAP: offset = (i*2**(self.size))%((2**self.size)*(self.len)) r += [Beat(self.addr + offset)] else: r += [Beat(self.addr)] return r class Beat: def __init__(self, addr): self.addr = addr class TestAXI(unittest.TestCase): def test_burst2beat(self): def bursts_generator(ax, bursts, valid_rand=50): prng = random.Random(42) for burst in bursts: yield ax.valid.eq(1) yield ax.addr.eq(burst.addr) yield ax.burst.eq(burst.type) yield ax.len.eq(burst.len) yield ax.size.eq(burst.size) while (yield ax.ready) == 0: yield yield ax.valid.eq(0) while prng.randrange(100) < valid_rand: yield yield @passive def beats_checker(ax, beats, ready_rand=50): self.errors = 0 yield ax.ready.eq(0) prng = random.Random(42) for beat in beats: while ((yield ax.valid) and (yield ax.ready)) == 0: if prng.randrange(100) > ready_rand: yield ax.ready.eq(1) else: yield ax.ready.eq(0) yield ax_addr = (yield ax.addr) if ax_addr != beat.addr: self.errors += 1 yield # dut ax_burst = stream.Endpoint(ax_description(32, 32)) ax_beat = stream.Endpoint(ax_description(32, 32)) dut = AXIBurst2Beat(ax_burst, ax_beat) # generate dut input (bursts) prng = random.Random(42) bursts = [] for i in range(32): bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8))) bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8))) bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2))) # generate expected dut output (beats for reference) beats = [] for burst in bursts: beats += burst.to_beats() # simulation generators = [ bursts_generator(ax_burst, bursts), beats_checker(ax_beat, beats) ] run_simulation(dut, generators) self.assertEqual(self.errors, 0)