from functools import partial

from migen.fhdl.structure import *
from migen.bank.description import *
from migen.bank import csrgen

class Inst:
	def __init__(self, address, clk_freq, baud=115200):
		self._rxtx = rxtx = Register("rxtx", BV(8))
		divisor = Register("divisor")
		self._f_divisor = Field(divisor, "divisor", 8) # TODO: 16
		stat = Register("stat") # TODO: autogenerated event manager
		self._f_thre = Field(stat, "thre", access_bus=READ_ONLY, access_dev=WRITE_ONLY)
		
		self.bank = csrgen.Bank([rxtx, divisor, stat], address=address)
		d = partial(declare_signal, self)
		d("tx", reset=1)
		d("rx")
		
		d("_enable16")
		d("_enable16_counter", BV(16))
		d("_tx_reg", BV(8))
		d("_tx_bitcount", BV(4))
		d("_tx_count16", BV(4))
		d("_tx_busy")
		self.divisor = int(clk_freq/baud/16); # TODO
	
	def get_fragment(self):
		comb = [self._enable16.eq(self._enable16_counter == Constant(0, BV(16)))]
		sync = [self._enable16_counter.eq(self._enable16_counter - 1),
			If(self._enable16, self._enable16_counter.eq(self.divisor - 1))] # TODO
		
		sync += [If(self._rxtx.dev_re,
			self._tx_reg.eq(self._rxtx.dev_r),
			self._tx_bitcount.eq(0),
			self._tx_count16.eq(1),
			self._tx_busy.eq(1),
			self.tx.eq(0)
		).Elif(self._enable16 & self._tx_busy,
			self._tx_count16.eq(self._tx_count16 + 1),
			If(self._tx_count16 == Constant(0, BV(4)),
				self._tx_bitcount.eq(self._tx_bitcount + 1),
				If(self._tx_bitcount == 8,
					self.tx.eq(1)
				).Elif(self._tx_bitcount == 9,
					self.tx.eq(1),
					self._tx_busy.eq(0)
				).Else(
					self.tx.eq(self._tx_reg[0]),
					self._tx_reg.eq(Cat(self._tx_reg[1:], 0))
				)
			)
		)]
		
		comb += [self._f_thre.dev_we.eq(1), self._f_thre.dev_w.eq(~self._tx_busy)]
		return self.bank.get_fragment() + Fragment(comb, sync, pads={self.tx, self.rx})