#ifndef __HW_DVISAMPLER_H #define __HW_DVISAMPLER_H #include #include #define DVISAMPLER0_CSR(x) MMPTR(DVISAMPLER0_BASE+(x)) #define CSR_DVISAMPLER0_PLL_RESET DVISAMPLER0_CSR(0x00) #define CSR_DVISAMPLER0_PLL_LOCKED DVISAMPLER0_CSR(0x04) #define CSR_DVISAMPLER0_D0_DELAY_CTL DVISAMPLER0_CSR(0x08) #define CSR_DVISAMPLER0_D0_DELAY_BUSY DVISAMPLER0_CSR(0x0C) #define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10) #define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14) #define CSR_DVISAMPLER0_D0_CHAR_SYNCED DVISAMPLER0_CSR(0x18) #define CSR_DVISAMPLER0_D0_CTL_POS DVISAMPLER0_CSR(0x1C) #define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x20) #define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x24) #define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x28) #define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x2C) #define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x30) #define CSR_DVISAMPLER0_D1_CTL_POS DVISAMPLER0_CSR(0x34) #define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x38) #define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x3C) #define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x40) #define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x44) #define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x48) #define CSR_DVISAMPLER0_D2_CTL_POS DVISAMPLER0_CSR(0x4C) #define CSR_DVISAMPLER0_CHAN_SYNCED DVISAMPLER0_CSR(0x50) #define CSR_DVISAMPLER0_HRESH DVISAMPLER0_CSR(0x54) #define CSR_DVISAMPLER0_HRESL DVISAMPLER0_CSR(0x58) #define CSR_DVISAMPLER0_VRESH DVISAMPLER0_CSR(0x5C) #define CSR_DVISAMPLER0_VRESL DVISAMPLER0_CSR(0x60) #define CSR_DVISAMPLER0_DECNT2 DVISAMPLER0_CSR(0x64) #define CSR_DVISAMPLER0_DECNT1 DVISAMPLER0_CSR(0x68) #define CSR_DVISAMPLER0_DECNT0 DVISAMPLER0_CSR(0x6C) #define DVISAMPLER_DELAY_CAL 0x01 #define DVISAMPLER_DELAY_RST 0x02 #define DVISAMPLER_DELAY_INC 0x04 #define DVISAMPLER_DELAY_DEC 0x08 #define DVISAMPLER_TOO_LATE 0x01 #define DVISAMPLER_TOO_EARLY 0x02 #endif /* __HW_DVISAMPLER_H */