__   _ __      _______ _________
                     / /  (_) /____ / __/ _ /_  __/ _ |
                    / /__/ / __/ -_)\ \/ __ |/ / / __ |
                   /____/_/\__/\__/___/_/ |_/_/ /_/ |_|

        Copyright 2014-2015 / Florent Kermarrec / florent@enjoy-digital.fr

                A generic and configurable SATA1/2/3 core
              developed in partnership with M-Labs Ltd & HKU

[> Features
------------------
PHY:
  - OOB, COMWAKE, COMINIT.
  - ALIGN inserter/remover and bytes alignment on K28.5.
  - 8B/10B encoding/decoding in transceiver.
  - Errors detection and reporting.
  - 1.5  / 3.0 / 6.0GBPs supported speeds.
  - 37.5 /  75 / 150MHz system clock.
Core:
  Link:
    - CONT inserter/remover.
    - Scrambling/Descrambling of data.
    - CRC inserter/checker.
    - HOLD insertion/detection.
    - Errors detection and reporting.
  Transport/Command:
    - Easy to use user interface (Can be used with or without CPU).
    - 48 bits sector addressing.
    - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE.
    - Errors detection and reporting.

Frontend:
  - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
  - Ports arbitration transparent to the user.
  - Synthetizable BIST.

[> Getting started
------------------
1. Install Python3 and Xilinx's Vivado software.

2. Obtain Migen and install it:
  git clone https://github.com/enjoy-digital/migen
  cd migen
  python3 setup.py install
  cd ..

3. Obtain Miscope and install it:
  git clone https://github.com/enjoy-digital/miscope
  cd miscope
  python3 setup.py install
  cd ..

4. Obtain MiSoC:
  git clone https://github.com/enjoy-digital/misoc --recursive

5. Copy lite-sata in working directory and move to it.

6. Build and load design:
  make all

7. Test design:
  go to test directory and run:
  python3 bist.py

[> Simulations :
  Simulations are avalaible in ./lib/sata/test:
    - crc_tb
    - scrambler_tb
    - phy_datapath_tb
    - link_tb
    - command_tb
    - bist_tb
  hdd.py is a HDD model implementing all SATA layers.
  To run a simulation, move to ./lib/sata/test and run:
    make simulation_name

[> Tests :
  A synthetisable BIST is provided and can be controlled with ./test/bist.py
  By using Miscope and the provided ./test/test_link.py example you are able to
  visualize the internal logic of the design and even inject the captured data in
  the HDD model!

[> Contact
E-mail: florent@enjoy-digital.fr