__ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Migen inside Build your hardware, easily! Copyright 2012-2019 / EnjoyDigital [> Intro -------- LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs. LiteX is based on Migen and provides specific building/debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem. Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a toolbox to create/develop/debug FPGA SoCs in Python. Typical LiteX design flow: -------------------------- +---------------+ |FPGA toolchains| +----^-----+----+ | | +--+-----v--+ +-------+ | | | Migen +--------> | +-------+ | | Your design | LiteX +---> ready to be used! | | +----------------------+ | | |LiteX Cores Ecosystem +--> | +----------------------+ +-^-------^-+ (Eth, SATA, DRAM, USB, | | PCIe, Video, etc...) + + board target file file LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv and is compatible with the LiteX's Cores Ecosystem: - LiteDRAM: https://github.com/enjoy-digital/litedram - LiteEth: https://github.com/enjoy-digital/liteeth - LitePCIe: https://github.com/enjoy-digital/litepcie - LiteSATA: https://github.com/enjoy-digital/litesata - LiteUSB: https://github.com/enjoy-digital/liteusb - LiteSDCard: https://github.com/enjoy-digital/litesdcard - LiteICLink: https://github.com/enjoy-digital/liteiclink - LiteJESD204B: https://github.com/enjoy-digital/litejesd204b - LiteVideo: https://github.com/enjoy-digital/litevideo - LiteScope: https://github.com/enjoy-digital/litescope [> Sub-packages --------------- gen: Provides specific or experimental modules to generate HDL that are not integrated in Migen. build: Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs. soc: Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores. boards: Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. [> Very Quick start guide (for newcomers) ----------------------------------------- TimVideos.us has done an awesome job for setting up a LiteX environment easily in the litex-buildenv repo: https://github.com/timvideos/litex-buildenv It's recommended for newcomers to go this way. Various FPGA boards are supported and multiple examples provided! You can even run Linux on your FPGA using LiteX very easily! Migen documentation can be found here: https://m-labs.hk/migen/manual FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_101 [> Quick start guide (for advanced users) ----------------------------------------- 0. Install Python 3.5+ and FPGA vendor's development tools. 1. Get litex_setup.py script and execute: ./litex_setup.py init install This will clone and install Migen, LiteX and LiteX's cores. To update all repositories execute: ./litex_setup.py update 2. Compile and install binutils. Take the latest version from GNU. mkdir build && cd build ../configure --target=lm32-elf make make install 3. (Optional, only if you want to use a lm32 CPU in you SoC) Compile and install GCC. Take gcc-core and gcc-g++ from GNU (version 4.5 or >=4.9). rm -rf libstdc++-v3 mkdir build && cd build ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \ --disable-libssp make make install 4. Build the target of your board...: Go to boards/targets and execute the target you want to build 5. ... and/or install Verilator and test LiteX on your computer: Download and install Verilator: http://www.veripool.org/ On Fedora: sudo dnf install libevent-devel json-c-devel On Ubuntu: sudo apt install libevent-dev libjson-c-dev run: litex_sim 6. Run a terminal program on the board's serial port at 115200 8-N-1. You should get the BIOS prompt. [> Contact ---------- E-mail: florent [AT] enjoy-digital.fr