Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteEth footprint is really small!

LiteEth generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit user's needs! (Implement only the layers you need, store data in RAM or DMA, use full-hardware UDP/IP stack and so on...)

LiteEth can target all FPGAs regardless of the vendor, you only have to ensure that your PHY is available!