from migen.fhdl.std import * from migen.bank import csrgen from migen.bus import wishbone, csr from migen.bus import wishbone2csr from migen.genlib.resetsync import AsyncResetSynchronizer from miscope.uart2wishbone import UART2Wishbone from misoclib import identifier from lib.sata.k7sataphy import K7SATAPHY class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) clk200 = platform.request("clk200") clk200_se = Signal() self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se) pll_locked = Signal() pll_fb = Signal() pll_sys = Signal() self.specials += [ Instance("PLLE2_BASE", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, # VCO @ 1GHz p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0, p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, # 166.66MHz p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=, p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=, p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=, p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4= ), Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked), ] class UART2WB(Module): csr_base = 0x00000000 csr_data_width = 8 csr_map = { "uart2wb": 0, "identifier": 2, } interrupt_map = {} cpu_type = None def __init__(self, platform, clk_freq): self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq) # CSR bridge 0x00000000 (shadow @0x00000000) self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) self._wb_masters = [self.uart2wb.wishbone] self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] # CSR self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0) def add_wb_master(self, wbm): if self.finalized: raise FinalizeError self._wb_masters.append(wbm) def add_wb_slave(self, address_decoder, interface): if self.finalized: raise FinalizeError self._wb_slaves.append((address_decoder, interface)) def do_finalize(self): # Wishbone self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self._wb_slaves, register=True) # CSR self.submodules.csrbankarray = csrgen.BankArray(self, lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], data_width=self.csr_data_width) self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) class TestDesign(UART2WB): default_platform = "kc705" def __init__(self, platform): clk_freq = 166666*1000 UART2WB.__init__(self, platform, clk_freq) self.submodules.crg = _CRG(platform) self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True) self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False) default_subtarget = TestDesign