Thanks to simple and efficient Migen building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!

LiteSATA generates HDL using Migen, a Python-based logic design system. The core is easily configurable to fit user's needs! (number of crossbar ports, RAID configuration, included BIST and so on...)

Porting the core to another vendor or family only requires adapting or adding a new PHY. All others building blocks of the core are generic.