From 262da6444cd653eae57adc400ccaf8cea330deda Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Fri, 11 May 2018 23:27:53 +0200
Subject: [PATCH 1/3] Add FuseSoC .core file for SPI Flash model

This allows other cores to depend on spiflash. Can also be used to
run the spiflash testbench with

fusesoc run --tool=<tool> spiflash --firmware=path/to/firmware.hex

This has been tested with icarus, modelsim and xsim. Fails with isim
If --tool is left out, icarus will be used as default
---
 picosoc/spiflash.core | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 picosoc/spiflash.core

diff --git a/picosoc/spiflash.core b/picosoc/spiflash.core
new file mode 100644
index 0000000..1b7d153
--- /dev/null
+++ b/picosoc/spiflash.core
@@ -0,0 +1,24 @@
+CAPI=2:
+
+name : ::spiflash:0
+
+filesets:
+  model:
+    files : [spiflash.v]
+    file_type : verilogSource
+  tb:
+    files : [spiflash_tb.v]
+    file_type : verilogSource
+
+targets:
+  default:
+    default_tool : icarus
+    filesets : [model, "is_toplevel? (tb)"]
+    parameters : [firmware]
+    toplevel : [testbench]
+
+parameters :
+  firmware:
+    datatype    : file
+    description : Initial SPI Flash contents (in verilog hex format)
+    paramtype   : plusarg

From 80f128713d8183cd9b477754542d9bb321bc7f2b Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Fri, 11 May 2018 23:30:43 +0200
Subject: [PATCH 2/3] Add FuseSoC .core file for picosoc

This allows other cores to depend on the generic parts of picosoc
and use that as a base design.
---
 picosoc/picosoc.core | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 picosoc/picosoc.core

diff --git a/picosoc/picosoc.core b/picosoc/picosoc.core
new file mode 100644
index 0000000..a6eae08
--- /dev/null
+++ b/picosoc/picosoc.core
@@ -0,0 +1,23 @@
+CAPI=2:
+
+name : ::picosoc:0
+
+filesets:
+  picosoc:
+    files:
+      - simpleuart.v
+      - spimemio.v
+      - picosoc.v
+    file_type : verilogSource
+    depend : [picorv32]
+
+targets:
+  default:
+    filesets : [picosoc]
+    parameters : [PICORV32_REGS]
+
+parameters:
+  PICORV32_REGS:
+    datatype : str
+    default  : picosoc_regs
+    paramtype : vlogdefine

From 12274e9f8ab4cf50a3fb3c3a3068b1651be7f091 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Sat, 12 May 2018 22:11:30 +0200
Subject: [PATCH 3/3] Add FuseSoC .core file for hx8kdemo

The core file specifies targets for FPGA implementation (fusesoc
build hx8kdemo) and simulation (fusesoc run --tool=<tool>
--target=sim hx8kdemo --firmware=path/to/firmware.he).

Simulation has been tested successfully with icarus, modelsim and xsim
---
 picosoc/hx8kdemo.core | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 picosoc/hx8kdemo.core

diff --git a/picosoc/hx8kdemo.core b/picosoc/hx8kdemo.core
new file mode 100644
index 0000000..97a1989
--- /dev/null
+++ b/picosoc/hx8kdemo.core
@@ -0,0 +1,35 @@
+CAPI=2:
+
+name : ::hx8kdemo:0
+
+filesets:
+  hx8kdemo:
+    files: [hx8kdemo.v]
+    file_type : verilogSource
+    depend : [picosoc]
+  hx8ksim:
+    files:
+      - hx8kdemo_tb.v
+    file_type : verilogSource
+    depend : [spiflash, "yosys:techlibs:ice40"]
+
+  constraints:
+    files: [hx8kdemo.pcf]
+    file_type : PCF
+
+targets:
+  synth:
+    default_tool : icestorm
+    filesets : [constraints, hx8kdemo]
+    tools:
+      icestorm:
+        arachne_pnr_options : [-d, 8k]
+    toplevel : [hx8kdemo]
+  sim:
+    default_tool : icarus
+    filesets : [hx8kdemo, hx8ksim]
+    tools:
+      xsim:
+        xelab_options : [--timescale, 1ns/1ps]
+
+    toplevel : [testbench]