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picorv32
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Fix indenting in wishbone code

This commit is contained in:
Clifford Wolf 2017-03-14 11:51:09 +01:00
parent a25597532d
commit 3495604877
2 changed files with 122 additions and 137 deletions
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105
picorv32.v
View File

@ -2690,62 +2690,55 @@ module picorv32_wb #(
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i)
if (wb_rst_i)
begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end
else
begin
case (state)
IDLE:
if (mem_valid)
begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end
else
begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
WBSTART:
if (wbm_ack_i)
begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
WBEND:
begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
endcase
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule

154
testbench_wb.v
View File

@ -75,26 +75,25 @@ module picorv32_wrapper #(
irq[5] = &uut.picorv32_core.count_cycle[15:0];
end
wire [31:0] wb_m2s_adr;
wire [31:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we;
wire wb_m2s_cyc;
wire wb_m2s_stb;
//wire [2:0] wb_m2s_cti;
reg [2:0] wb_m2s_cti = 3'b000;
wire [1:0] wb_m2s_bte;
wire [31:0] wb_s2m_dat;
wire wb_s2m_ack;
wire wb_s2m_err;
wire wb_s2m_rty;
wire [31:0] wb_m2s_adr;
wire [31:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we;
wire wb_m2s_cyc;
wire wb_m2s_stb;
//wire [2:0] wb_m2s_cti;
reg [2:0] wb_m2s_cti = 3'b000;
wire [1:0] wb_m2s_bte;
wire [31:0] wb_s2m_dat;
wire wb_s2m_ack;
wire wb_s2m_err;
wire wb_s2m_rty;
wb_ram #(
.depth (16384 * 4),
.memfile ("firmware/firmware.hex"),
.VERBOSE (VERBOSE)
)
ram (// Wishbone interface
) ram ( // Wishbone interface
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
@ -111,7 +110,7 @@ wire wb_s2m_rty;
.wb_err_o(),
.tests_passed(tests_passed)
);
);
picorv32_wb #(
`ifndef SYNTH_TEST
@ -166,34 +165,33 @@ wire wb_s2m_rty;
end
endmodule
module wb_ram
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = 32,
parameter memfile = "",
parameter VERBOSE = 0
)
(
input wb_clk_i,
input wb_rst_i,
module wb_ram #(
//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = 32,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output reg [dw-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output reg [dw-1:0] wb_dat_o,
output reg tests_passed
);
output reg tests_passed
);
localparam CLASSIC_CYCLE = 1'b0;
localparam BURST_CYCLE = 1'b1;
@ -214,40 +212,40 @@ module wb_ram
BTE_WRAP_16 = 2'd3;
function wb_is_last;
input [2:0] cti;
begin
case (cti)
CTI_CLASSIC : wb_is_last = 1'b1;
CTI_CONST_BURST : wb_is_last = 1'b0;
CTI_INC_BURST : wb_is_last = 1'b0;
CTI_END_OF_BURST : wb_is_last = 1'b1;
default : $display("%d : Illegal Wishbone B3 cycle type (%b)", $time, cti);
endcase
end
input [2:0] cti;
begin
case (cti)
CTI_CLASSIC : wb_is_last = 1'b1;
CTI_CONST_BURST : wb_is_last = 1'b0;
CTI_INC_BURST : wb_is_last = 1'b0;
CTI_END_OF_BURST : wb_is_last = 1'b1;
default : $display("%d : Illegal Wishbone B3 cycle type (%b)", $time, cti);
endcase
end
endfunction
function [31:0] wb_next_adr;
input [31:0] adr_i;
input [2:0] cti_i;
input [2:0] bte_i;
input integer dw;
input [31:0] adr_i;
input [2:0] cti_i;
input [2:0] bte_i;
input integer dw;
reg [31:0] adr;
integer shift;
begin
shift = $clog2(dw/8);
adr = adr_i >> shift;
if (cti_i == CTI_INC_BURST)
case (bte_i)
BTE_LINEAR : adr = adr + 1;
BTE_WRAP_4 : adr = {adr[31:2], adr[1:0]+2'd1};
BTE_WRAP_8 : adr = {adr[31:3], adr[2:0]+3'd1};
BTE_WRAP_16 : adr = {adr[31:4], adr[3:0]+4'd1};
endcase // case (burst_type_i)
reg [31:0] adr;
integer shift;
begin
shift = $clog2(dw/8);
adr = adr_i >> shift;
if (cti_i == CTI_INC_BURST)
case (bte_i)
BTE_LINEAR : adr = adr + 1;
BTE_WRAP_4 : adr = {adr[31:2], adr[1:0]+2'd1};
BTE_WRAP_8 : adr = {adr[31:3], adr[2:0]+3'd1};
BTE_WRAP_16 : adr = {adr[31:4], adr[3:0]+4'd1};
endcase // case (burst_type_i)
wb_next_adr = adr << shift;
end
endfunction
wb_next_adr = adr << shift;
end
endfunction
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
@ -269,8 +267,7 @@ endfunction
wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
always @(posedge wb_clk_i)
begin
always @(posedge wb_clk_i) begin
adr_r <= adr;
valid_r <= valid;
// Ack generation
@ -308,9 +305,7 @@ endfunction
end
always @(posedge wb_clk_i) begin
if (waddr2 < 64 * 1024 / 4)
begin
if (waddr2 < 64 * 1024 / 4) begin
if (we[0])
mem[waddr2][7:0] <= wb_dat_i[7:0];
@ -336,11 +331,8 @@ endfunction
wb_dat_o <= mem[raddr2];
end
generate
initial
if (memfile != "") begin
initial begin
if (memfile != "")
$readmemh(memfile, mem);
end
endgenerate
end
endmodule