From 5c0e13779210983fb20d908085df4f43037ec132 Mon Sep 17 00:00:00 2001 From: Guy Hutchison Date: Thu, 18 Oct 2018 20:51:40 +0000 Subject: [PATCH] Removed dead code and cleanup before pull request --- scripts/romload/Makefile | 14 +------- scripts/romload/map2debug.py | 4 ++- scripts/romload/{sections.lds => sections.ld} | 4 +-- scripts/romload/start.S | 35 +------------------ scripts/romload/testbench.v | 17 +++++---- 5 files changed, 16 insertions(+), 58 deletions(-) rename scripts/romload/{sections.lds => sections.ld} (92%) diff --git a/scripts/romload/Makefile b/scripts/romload/Makefile index 8db733f..17f27ec 100644 --- a/scripts/romload/Makefile +++ b/scripts/romload/Makefile @@ -14,24 +14,16 @@ test: testbench.vvp firmware32.hex vvp -l testbench.log -N testbench.vvp testbench.vvp: testbench.v ../../picorv32.v firmware_dbg.v - iverilog -D WRITE_VCD=1 -o testbench.vvp testbench.v ../../picorv32.v + iverilog -o testbench.vvp testbench.v ../../picorv32.v chmod -x testbench.vvp firmware32.hex: firmware.elf hex8tohex32.py $(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp python3 hex8tohex32.py firmware.tmp > firmware32.hex -#firmware32.hex: firmware.elf start.elf hex8tohex32.py -# $(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp -# $(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp -# cat start.tmp firmware.tmp > firmware.hex -# python3 hex8tohex32.py firmware.hex > firmware32.hex -# rm -f start.tmp firmware.tmp firmware_dbg.v: firmware.map python3 map2debug.py -#firmware.o: firmware.c -# $(CC) -c $^ start.o: start.S $(CC) -c -nostdlib start.S $(LDLIBS) @@ -40,10 +32,6 @@ firmware.elf: firmware.o syscalls.o start.o $(CC) $(LDFLAGS),-Map=firmware.map -o $@ $^ -T sections.lds $(LDLIBS) chmod -x firmware.elf -start.elf: start.S start.ld - $(CC) -nostdlib -o start.elf start.S -T start.ld $(LDLIBS) - chmod -x start.elf - clean: rm -f *.o *.d *.tmp start.elf rm -f firmware.elf firmware.hex firmware32.hex diff --git a/scripts/romload/map2debug.py b/scripts/romload/map2debug.py index a79af05..fc5c97c 100644 --- a/scripts/romload/map2debug.py +++ b/scripts/romload/map2debug.py @@ -2,7 +2,7 @@ import re -symbol = re.compile("\s*0x([0-9a-f]+)\s+([\w_]+)\s*$") +symbol = re.compile("\s*0x([0-9a-f]+)\s+([\w_]+)") symbol_map = {} with open("firmware.map", "r") as fh: for fd in fh: @@ -12,6 +12,8 @@ with open("firmware.map", "r") as fh: symbol_map[addr] = sym.group(2) with open("firmware_dbg.v", "w") as fh: + for k, v in symbol_map.items(): + fh.write("`define C_SYM_{1:s} 32'h{0:08x}\n".format(k, v.upper())) fh.write(" task firmware_dbg;\n") fh.write(" input [31:0] addr;\n"); fh.write(" begin\n"); diff --git a/scripts/romload/sections.lds b/scripts/romload/sections.ld similarity index 92% rename from scripts/romload/sections.lds rename to scripts/romload/sections.ld index accb2c0..2ec3954 100644 --- a/scripts/romload/sections.lds +++ b/scripts/romload/sections.ld @@ -7,13 +7,12 @@ binary, for any purpose, commercial or non-commercial, and by any means. */ +/* starting address needs to be > 0 due to known bug in RISCV/GNU linker */ MEMORY { rom(rwx) : ORIGIN = 0x00000100, LENGTH = 63k ram(rwx) : ORIGIN = 0x00020000, LENGTH = 16k } -C_STACK_SIZE = 512; - ENTRY(_pvstart); SECTIONS { @@ -34,7 +33,6 @@ SECTIONS { . = ALIGN(4); _edata = .; } >ram AT>rom - /* } >ram */ .bss : { _bss_start = .; diff --git a/scripts/romload/start.S b/scripts/romload/start.S index 3561384..be59808 100644 --- a/scripts/romload/start.S +++ b/scripts/romload/start.S @@ -1,8 +1,6 @@ .section .text .global _start .global _pvstart -.global _data -.global _data_lma _pvstart: /* zero-initialize all registers */ @@ -42,10 +40,7 @@ addi x31, zero, 0 lui sp, %hi(4*1024*1024) addi sp, sp, %lo(4*1024*1024) -/* -lui sp, %hi(0x100000) -addi sp, sp, %lo(0x100000) -*/ + /* push zeros on the stack for argc and argv */ /* (stack is aligned to 16 bytes in riscv calling convention) */ addi sp,sp,-16 @@ -54,32 +49,4 @@ sw zero,4(sp) sw zero,8(sp) sw zero,12(sp) -/* - // Load data section - la a0, _data_lma - la a1, _data - la a2, _edata - bgeu a1, a2, 2f -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b -2: - - // Clear bss section - la a0, _bss_start - la a1, _bss_end - bgeu a0, a1, 2f -1: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, 1b -2: -*/ - -/* jump to libc init */ -/*j _ftext - */ j _start diff --git a/scripts/romload/testbench.v b/scripts/romload/testbench.v index 8c79e9b..e38819d 100644 --- a/scripts/romload/testbench.v +++ b/scripts/romload/testbench.v @@ -3,8 +3,9 @@ //`undef WRITE_VCD `undef MEM8BIT +// define the size of our ROM +// simulates ROM by suppressing writes below this address `define ROM_SIZE 32'h0001_00FF -//`define ROM_SIZE 32'h0000_0000 module testbench; reg clk = 1; @@ -52,10 +53,10 @@ module testbench; end `else reg [31:0] memory [0:MEM_SIZE/4-1]; -`define data_lma 32'hc430 -`define data 32'h20000 -`define edata 32'h209b0 integer x; + + // simulate hardware assist of clearing RAM and copying ROM data into + // memory initial begin // clear memory @@ -63,8 +64,8 @@ module testbench; // load rom contents $readmemh("firmware32.hex", memory); // copy .data section - for (x=0; x<(`edata - `data); x=x+4) - memory[(`data+x)/4] = memory[(`data_lma+x)/4]; + for (x=0; x<(`C_SYM__BSS_START - `C_SYM___GLOBAL_POINTER); x=x+4) + memory[(`C_SYM___GLOBAL_POINTER+x)/4] = memory[(`C_SYM__DATA_LMA+x)/4]; end `endif @@ -101,7 +102,9 @@ module testbench; endcase end if (mem_valid && mem_ready) begin - // firmware_dbg(mem_addr); +`ifdef FIRMWARE_DEBUG_ADDR + firmware_dbg(mem_addr); +`endif if ((mem_wstrb == 4'h0) && (mem_rdata === 32'bx)) $display("READ FROM UNITIALIZED ADDR=%x", mem_addr); `ifdef VERBOSE_MEM if (|mem_wstrb)