From 6edd0bfe141913e805b3456cd44f0c0e92f01c83 Mon Sep 17 00:00:00 2001
From: Tom Verbeure <hombre+github@gmail.com>
Date: Sun, 18 Aug 2019 08:32:45 -0700
Subject: [PATCH] Add tracing support to dhrystone test

---
 dhrystone/Makefile    |  4 ++++
 dhrystone/testbench.v | 26 ++++++++++++++++++++++++--
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/dhrystone/Makefile b/dhrystone/Makefile
index e66f313..4dc0361 100644
--- a/dhrystone/Makefile
+++ b/dhrystone/Makefile
@@ -13,6 +13,10 @@ endif
 test: testbench.vvp dhry.hex
 	vvp -N testbench.vvp
 
+test_trace: testbench.vvp dhry.hex
+	vvp -N $< +trace
+	python3 ../showtrace.py testbench.trace dhry.elf > testbench.ins
+
 test_nola: testbench_nola.vvp dhry.hex
 	vvp -N testbench_nola.vvp
 
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v
index 7744b0d..9c365a6 100644
--- a/dhrystone/testbench.v
+++ b/dhrystone/testbench.v
@@ -26,12 +26,16 @@ module testbench;
 	wire [31:0] mem_la_wdata;
 	wire [3:0] mem_la_wstrb;
 
+	wire trace_valid;
+	wire [35:0] trace_data;
+
 	picorv32 #(
 		.BARREL_SHIFTER(1),
 		.ENABLE_FAST_MUL(1),
 		.ENABLE_DIV(1),
 		.PROGADDR_RESET('h10000),
-		.STACKADDR('h10000)
+		.STACKADDR('h10000),
+		.ENABLE_TRACE(1)
 	) uut (
 		.clk         (clk        ),
 		.resetn      (resetn     ),
@@ -47,7 +51,9 @@ module testbench;
 		.mem_la_write(mem_la_write),
 		.mem_la_addr (mem_la_addr ),
 		.mem_la_wdata(mem_la_wdata),
-		.mem_la_wstrb(mem_la_wstrb)
+		.mem_la_wstrb(mem_la_wstrb),
+		.trace_valid (trace_valid),
+		.trace_data  (trace_data )
 	);
 
 	reg [7:0] memory [0:256*1024-1];
@@ -83,6 +89,22 @@ module testbench;
 		$dumpvars(0, testbench);
 	end
 
+	integer trace_file;
+
+	initial begin
+		if ($test$plusargs("trace")) begin
+			trace_file = $fopen("testbench.trace", "w");
+			repeat (10) @(posedge clk);
+			while (!trap) begin
+				@(posedge clk);
+				if (trace_valid)
+					$fwrite(trace_file, "%x\n", trace_data);
+			end
+			$fclose(trace_file);
+			$display("Finished writing testbench.trace.");
+		end
+	end
+
 	always @(posedge clk) begin
 		if (resetn && trap) begin
 			repeat (10) @(posedge clk);