From 727f2fbfbb827a70b7c8bb85561d524bcb699c77 Mon Sep 17 00:00:00 2001 From: Sebastian Zanker Date: Wed, 16 Dec 2020 09:00:03 +0100 Subject: [PATCH] Update picorv32.v Clocked process for the AXI_BREADY signal. --- picorv32.v | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/picorv32.v b/picorv32.v index 6364cbe..457fdc4 100644 --- a/picorv32.v +++ b/picorv32.v @@ -2764,6 +2764,8 @@ module picorv32_axi_adapter ( reg ack_arvalid; reg ack_wvalid; reg xfer_done; + + reg axi_bready; assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid; assign mem_axi_awaddr = mem_addr; @@ -2778,9 +2780,21 @@ module picorv32_axi_adapter ( assign mem_axi_wstrb = mem_wstrb; assign mem_ready = mem_axi_bvalid || mem_axi_rvalid; - assign mem_axi_bready = mem_valid && |mem_wstrb; + //assign mem_axi_bready = mem_valid && |mem_wstrb; assign mem_axi_rready = mem_valid && !mem_wstrb; assign mem_rdata = mem_axi_rdata; + + // control logic for AXI_BREADY + always @(posedge clk) begin : AXI_BREADY_p + axi_bready <= 1'b0; + if (mem_axi_bvalid && mem_valid && |mem_wstrb && ~axi_bready) begin + axi_bready <= 1'b1; + end else begin + axi_bready <= 1'b0; + end + end + + assign mem_axi_bready = axi_bready; always @(posedge clk) begin if (!resetn) begin @@ -2802,7 +2816,6 @@ module picorv32_axi_adapter ( end endmodule - /*************************************************************** * picorv32_wb ***************************************************************/