diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 0000000..0285421 --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,25 @@ +name: build-openlane-sky130 +on: [push] + +jobs: + build-picorv32: + runs-on: ubuntu-latest + steps: + - name: Checkout repo + uses: actions/checkout@v2 + with: + path: picorv32 + - name: Checkout pdk + uses: actions/checkout@v2 + with: + repository: olofk/pdklite + path: pdklite + - run: echo "PDK_ROOT=$GITHUB_WORKSPACE/pdklite" >> $GITHUB_ENV + - run: echo "EDALIZE_LAUNCHER=${GITHUB_WORKSPACE}/openlane_runner.py" >> $GITHUB_ENV + - run: pip3 install --user -e "git+https://github.com/olofk/edalize.git#egg=edalize" + - run: pip3 install fusesoc + - run: docker pull efabless/openlane:v0.12 + - run: wget https://raw.githubusercontent.com/olofk/subservient/main/openlane_runner.py + - run: chmod +x openlane_runner.py + - run: fusesoc library add fpganes $GITHUB_WORKSPACE/picorv32 + - run: fusesoc run --target=sky130 picorv32 \ No newline at end of file diff --git a/openlane_params.tcl b/openlane_params.tcl new file mode 100644 index 0000000..494da22 --- /dev/null +++ b/openlane_params.tcl @@ -0,0 +1,8 @@ +# These values are taken from the designs examples in the Openlane repository +set ::env(CLOCK_PORT) "clk" +set ::env(CLOCK_NET) $::env(CLOCK_PORT) +set ::env(GLB_RT_ADJUSTMENT) 0.1 +set ::env(SYNTH_MAX_FANOUT) 6 +set ::env(CLOCK_PERIOD) "24.73" +set ::env(FP_CORE_UTIL) 30 +set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ] \ No newline at end of file diff --git a/picorv32.core b/picorv32.core index 08ee704..579bace 100644 --- a/picorv32.core +++ b/picorv32.core @@ -1,5 +1,5 @@ CAPI=2: -name : ::picorv32:0-r1 +name : ::picorv32:1.0 filesets: rtl: @@ -18,6 +18,9 @@ filesets: tb_verilator: files: - testbench.cc : {file_type : cppSource} + openlane: + files: + - openlane_params.tcl : {file_type : tclSource} targets: default: @@ -29,6 +32,19 @@ targets: verilator: mode : lint-only toplevel : [picorv32_axi] + + sky130: + default_tool : openlane + filesets : [rtl, openlane] + parameters : + - ENABLE_REGS_16_31=0 + - ENABLE_REGS_DUALPORT=0 + - BARREL_SHIFTER=1 + - TWO_CYCLE_ALU=1 + - ENABLE_FAST_MUL=1 + - ENABLE_IRQ=1 + toplevel : picorv32 + test: default_tool: icarus filesets: [rtl, tb, "tool_verilator? (tb_verilator)"] @@ -36,7 +52,7 @@ targets: toplevel: - "tool_verilator? (picorv32_wrapper)" - "!tool_verilator? (testbench)" - + tools: verilator : cli_parser : fusesoc @@ -58,6 +74,24 @@ parameters: datatype : str default : 1 paramtype : vlogdefine + ENABLE_REGS_16_31: + datatype : int + paramtype : vlogparam + ENABLE_REGS_DUALPORT: + datatype : int + paramtype : vlogparam + BARREL_SHIFTER: + datatype : int + paramtype : vlogparam + TWO_CYCLE_ALU: + datatype : int + paramtype : vlogparam + ENABLE_FAST_MUL: + datatype : int + paramtype : vlogparam + ENABLE_IRQ: + datatype : int + paramtype : vlogparam axi_test: datatype : bool paramtype : plusarg @@ -75,4 +109,4 @@ parameters: paramtype : plusarg verbose: datatype : bool - paramtype : plusarg + paramtype : plusarg \ No newline at end of file