From 997c5ce341ce4fcc209992a9b9096651e767eb2d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Jun 2015 01:46:25 +0200
Subject: [PATCH] Added "make test_synth"

---
 .gitignore                 |  3 +++
 Makefile                   | 14 ++++++++++++--
 scripts/yosys/synth_sim.ys |  7 +++++++
 3 files changed, 22 insertions(+), 2 deletions(-)
 create mode 100644 scripts/yosys/synth_sim.ys

diff --git a/.gitignore b/.gitignore
index 5eea6b0..0db16ed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -17,5 +17,8 @@
 /testbench.exe
 /testbench_sp.exe
 /testbench_axi.exe
+/testbench_synth.exe
 /testbench.vcd
+/synth.log
+/synth.v
 .*.swp
diff --git a/Makefile b/Makefile
index 909f0ae..6976538 100644
--- a/Makefile
+++ b/Makefile
@@ -11,6 +11,9 @@ test_sp: testbench_sp.exe firmware/firmware.hex
 test_axi: testbench_axi.exe firmware/firmware.hex
 	vvp -N testbench_axi.exe
 
+test_synth: testbench_synth.exe firmware/firmware.hex
+	vvp -N testbench_synth.exe
+
 testbench.exe: testbench.v picorv32.v
 	iverilog -o testbench.exe testbench.v picorv32.v
 	chmod -x testbench.exe
@@ -23,6 +26,13 @@ testbench_axi.exe: testbench.v picorv32.v
 	iverilog -o testbench_axi.exe -DAXI_TEST testbench.v picorv32.v
 	chmod -x testbench_axi.exe
 
+testbench_synth.exe: testbench.v synth.v
+	iverilog -o testbench_synth.exe testbench.v synth.v
+	chmod -x testbench_synth.exe
+
+synth.v: picorv32.v scripts/yosys/synth_sim.ys
+	yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
+
 firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
 	python3 firmware/makehex.py $< > $@
 
@@ -48,8 +58,8 @@ tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
 
 clean:
 	rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) \
-		firmware/firmware.{elf,bin,hex,map} \
-		testbench{,_sp,_axi}.exe testbench.vcd
+		firmware/firmware.{elf,bin,hex,map} synth.v \
+		testbench{,_sp,_axi,_synth}.exe testbench.vcd
 
 .PHONY: test test_sp test_axi clean
 
diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys
new file mode 100644
index 0000000..b64e7e1
--- /dev/null
+++ b/scripts/yosys/synth_sim.ys
@@ -0,0 +1,7 @@
+# yosys synthesis script for post-synthesis simulation (make test_synth)
+
+read_verilog picorv32.v
+chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
+hierarchy -top picorv32_axi
+synth
+write_verilog synth.v