From 9a5d35c19559a65826ea42d575d8085a682b94f6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 10 Apr 2016 12:35:16 +0200 Subject: [PATCH] Using Verilator in torture test bench --- scripts/torture/.gitignore | 1 + scripts/torture/Makefile | 16 +++++++++++++--- scripts/torture/testbench.cc | 18 ++++++++++++++++++ scripts/torture/testbench.v | 25 ++++++++++++++----------- 4 files changed, 46 insertions(+), 14 deletions(-) create mode 100644 scripts/torture/testbench.cc diff --git a/scripts/torture/.gitignore b/scripts/torture/.gitignore index a1de2e4..a9db520 100644 --- a/scripts/torture/.gitignore +++ b/scripts/torture/.gitignore @@ -2,6 +2,7 @@ riscv-fesvr riscv-isa-sim riscv-torture +obj_dir tests test.S test.elf diff --git a/scripts/torture/Makefile b/scripts/torture/Makefile index e9bea89..38051f0 100644 --- a/scripts/torture/Makefile +++ b/scripts/torture/Makefile @@ -1,4 +1,10 @@ +# Icarus Verilog +#TESTBENCH_EXE = tests/testbench.vvp + +# Verilator +TESTBENCH_EXE = obj_dir/Vtestbench + test: riscv-torture/build.ok riscv-isa-sim/build.ok bash test.sh @@ -28,6 +34,10 @@ batch_list = $(shell bash -c 'for i in {0..999}; do printf "%03d\n" $$i; done') batch: $(addprefix tests/test_,$(addsuffix .ok,$(batch_list))) +obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v + verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc + $(MAKE) -C obj_dir -f Vtestbench.mk + tests/testbench.vvp: testbench.v ../../picorv32.v mkdir -p tests iverilog -o tests/testbench.vvp testbench.v ../../picorv32.v @@ -55,8 +65,8 @@ tests/test_$(1).hex: tests/test_$(1).bin tests/test_$(1).ref: tests/test_$(1).elf riscv-isa-sim/build.ok LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike tests/test_$(1).elf > tests/test_$(1).ref -tests/test_$(1).ok: tests/testbench.vvp tests/test_$(1).hex tests/test_$(1).ref - vvp tests/testbench.vvp +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref | tee tests/test_$(1).out +tests/test_$(1).ok: $(TESTBENCH_EXE) tests/test_$(1).hex tests/test_$(1).ref + $(TESTBENCH_EXE) +hex=tests/test_$(1).hex +ref=tests/test_$(1).ref | tee tests/test_$(1).out grep -q PASSED tests/test_$(1).out mv tests/test_$(1).out tests/test_$(1).ok endef @@ -71,7 +81,7 @@ loop: done clean: - rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests + rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests obj_dir rm -f test.S test.elf test.bin test.hex test.ref test.vvp .PHONY: test batch loop clean diff --git a/scripts/torture/testbench.cc b/scripts/torture/testbench.cc new file mode 100644 index 0000000..2925d0b --- /dev/null +++ b/scripts/torture/testbench.cc @@ -0,0 +1,18 @@ +#include "Vtestbench.h" +#include "verilated.h" + +int main(int argc, char **argv, char **env) +{ + Verilated::commandArgs(argc, argv); + Vtestbench* top = new Vtestbench; + + top->clk = 0; + while (!Verilated::gotFinish()) { + top->clk = !top->clk; + top->eval(); + } + + delete top; + exit(0); +} + diff --git a/scripts/torture/testbench.v b/scripts/torture/testbench.v index 41f3495..088b7aa 100644 --- a/scripts/torture/testbench.v +++ b/scripts/torture/testbench.v @@ -33,25 +33,20 @@ module testbench ( .mem_rdata (mem_rdata ) ); - reg [1023:0] hex_filename; - reg [1023:0] ref_filename; + localparam integer filename_len = 18; + reg [8*filename_len-1:0] hex_filename; + reg [8*filename_len-1:0] ref_filename; reg [31:0] memory [0:4095]; reg [31:0] memory_ref [0:4095]; integer i, errcount; + integer cycle = 0; initial begin if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory); if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref); // $dumpfile("testbench.vcd"); // $dumpvars(0, testbench); - - repeat (10) @(posedge clk); - resetn <= 1; - - repeat (100000) @(posedge clk); - $display("FAILED: Timeout!"); - $finish; end always @(posedge clk) begin @@ -79,10 +74,18 @@ module testbench ( end end if (errcount) - $display("FAILED: Got %1d errors for %1s => %1s!", errcount, hex_filename, ref_filename); + $display("FAILED: Got %1d errors for %s => %s!", errcount, hex_filename, ref_filename); else - $display("PASSED %1s => %1s.", hex_filename, ref_filename); + $display("PASSED %s => %s.", hex_filename, ref_filename); $finish; end + + if (cycle > 100000) begin + $display("FAILED: Timeout!"); + $finish; + end + + resetn <= cycle > 10; + cycle <= cycle + 1; end endmodule