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Fix simpleuart baud rate calculation 

This patch fixes the baud rate calculation so that the behavior of
simpleuart is in line with the description in picosoc/README.md:

> The UART Clock Divider Register must be set to the system clock
> frequency divided by the baud rate.

Previously, the effective behavior of simpleuart was

    divisor = (clock frequency / baud rate) - 2

The fix is done basically by comparing `*_divcnt + 1 >= cfg_divider`
instead of the old `*_divcnt > cfg_divider`. A special case is needed in
the receive logic for the case where the divider is equal to 1, where at
the next cycle we want to read the first bit (jumping straight to a
`recv_state` of 2).

This patch also makes some minor stylistic changes that fix Verilator
lint errors.
This commit is contained in:
Anish Athalye 2020-05-02 11:14:18 -04:00
parent f9b1beb4cf
commit 9aae9632d9
1 changed files with 11 additions and 11 deletions
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22
picosoc/simpleuart.v
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@ -49,8 +49,8 @@ module simpleuart #(parameter integer DEFAULT_DIV = 1) (
assign reg_div_do = cfg_divider; assign reg_div_do = cfg_divider;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); assign reg_dat_wait = reg_dat_we && (send_bitcnt != 4'h0 || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; assign reg_dat_do = recv_buf_valid ? {24'h0, recv_buf_data} : ~0;
always @(posedge clk) begin always @(posedge clk) begin
if (!resetn) begin if (!resetn) begin
@ -77,24 +77,24 @@ module simpleuart #(parameter integer DEFAULT_DIV = 1) (
case (recv_state) case (recv_state)
0: begin 0: begin
if (!ser_rx) if (!ser_rx)
recv_state <= 1; recv_state <= cfg_divider == 32'h1 ? 2 : 1;
recv_divcnt <= 0; recv_divcnt <= 1;
end end
1: begin 1: begin
if (2*recv_divcnt > cfg_divider) begin if (2*recv_divcnt >= cfg_divider) begin
recv_state <= 2; recv_state <= 2;
recv_divcnt <= 0; recv_divcnt <= 0;
end end
end end
10: begin 10: begin
if (recv_divcnt > cfg_divider) begin if (recv_divcnt + 1 >= cfg_divider) begin
recv_buf_data <= recv_pattern; recv_buf_data <= recv_pattern;
recv_buf_valid <= 1; recv_buf_valid <= 1;
recv_state <= 0; recv_state <= 0;
end end
end end
default: begin default: begin
if (recv_divcnt > cfg_divider) begin if (recv_divcnt + 1 >= cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]}; recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1; recv_state <= recv_state + 1;
recv_divcnt <= 0; recv_divcnt <= 0;
@ -107,7 +107,7 @@ module simpleuart #(parameter integer DEFAULT_DIV = 1) (
assign ser_tx = send_pattern[0]; assign ser_tx = send_pattern[0];
always @(posedge clk) begin always @(posedge clk) begin
if (reg_div_we) if (| reg_div_we)
send_dummy <= 1; send_dummy <= 1;
send_divcnt <= send_divcnt + 1; send_divcnt <= send_divcnt + 1;
if (!resetn) begin if (!resetn) begin
@ -116,18 +116,18 @@ module simpleuart #(parameter integer DEFAULT_DIV = 1) (
send_divcnt <= 0; send_divcnt <= 0;
send_dummy <= 1; send_dummy <= 1;
end else begin end else begin
if (send_dummy && !send_bitcnt) begin if (send_dummy && send_bitcnt == 4'h0) begin
send_pattern <= ~0; send_pattern <= ~0;
send_bitcnt <= 15; send_bitcnt <= 15;
send_divcnt <= 0; send_divcnt <= 0;
send_dummy <= 0; send_dummy <= 0;
end else end else
if (reg_dat_we && !send_bitcnt) begin if (reg_dat_we && send_bitcnt == 4'h0) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10; send_bitcnt <= 10;
send_divcnt <= 0; send_divcnt <= 0;
end else end else
if (send_divcnt > cfg_divider && send_bitcnt) begin if (send_divcnt + 1 >= cfg_divider && send_bitcnt != 4'h0) begin
send_pattern <= {1'b1, send_pattern[9:1]}; send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1; send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0; send_divcnt <= 0;