From abe046575321153c0bed10525fe8d12b92e776b1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 6 Jun 2015 19:35:07 +0200
Subject: [PATCH] Faster memory model in dhrystone testbench

---
 dhrystone/testbench.v | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v
index ab0594c..1e2de3d 100644
--- a/dhrystone/testbench.v
+++ b/dhrystone/testbench.v
@@ -14,11 +14,11 @@ module testbench;
 
 	wire mem_valid;
 	wire mem_instr;
-	reg mem_ready;
+	wire mem_ready;
 	wire [31:0] mem_addr;
 	wire [31:0] mem_wdata;
 	wire [3:0] mem_wstrb;
-	reg [31:0] mem_rdata;
+	wire [31:0] mem_rdata;
 
 	picorv32 uut (
 		.clk      (clk      ),
@@ -36,23 +36,23 @@ module testbench;
 	reg [31:0] memory [0:64*1024/4-1];
 	initial $readmemh("dhry.hex", memory);
 
+	assign mem_ready = 1;
+	assign mem_rdata = memory[mem_addr >> 2];
+
 	always @(posedge clk) begin
-		mem_ready <= 0;
-		mem_rdata <= 'bx;
-		if (resetn && mem_valid && !mem_ready) begin
-			mem_ready <= 1;
-			if (mem_addr == 32'h1000_0000) begin
-				$write("%c", mem_wdata);
-				$fflush();
-			end else
-			if (mem_wstrb) begin
-				if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
-				if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
-				if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
-				if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
-			end else begin
-				mem_rdata <= memory[mem_addr >> 2];
-			end
+		if (mem_valid) begin
+			case (mem_addr)
+				32'h1000_0000: begin
+					$write("%c", mem_wdata);
+					$fflush();
+				end
+				default: begin
+					if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
+					if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
+					if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
+					if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
+				end
+			endcase
 		end
 	end