From b076d72806fb84ee0557a75f871aef0ba0d6a66b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 28 Jun 2015 14:51:53 +0200 Subject: [PATCH] Fixed PCPI instr prefetching --- README.md | 7 ++++--- picorv32.v | 3 +-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 298b272..958d3b7 100644 --- a/README.md +++ b/README.md @@ -195,7 +195,7 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT. | shift operations | 4-14 | 4-15 | When `ENABLE_MUL` is activated, then a `MUL` instruction will execute -in 42 cycles and a `MULH[SU|U]` instruction will execute in 74 cycles. +in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles. Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz) @@ -405,12 +405,13 @@ enabled PCPI, IRQ and MUL features. | PicoRV32 "regular" | 996 | 48 | | PicoRV32 "large" | 1814 | 88 | +*Note: Most of the size reduction in the "small" core comes from eliminating +the counter instructions, not from reducing the size of the register file.* + Todos: ------ -- Optional FENCE support -- Optional write-through cache - Optional support for compressed ISA - Improved documentation and examples diff --git a/picorv32.v b/picorv32.v index abccc23..b09c709 100644 --- a/picorv32.v +++ b/picorv32.v @@ -164,8 +164,7 @@ module picorv32 #( reg mem_do_wdata; wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata}; - - wire mem_done = mem_ready && ((mem_state[0] && (mem_do_rinst || mem_do_rdata)) || mem_state == 2); + wire mem_done = (mem_ready && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst); assign mem_la_write = resetn && !mem_state && mem_do_wdata; assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);