From bdbcb57ac8cb8b1cdbc42e29feef947640c09ee6 Mon Sep 17 00:00:00 2001
From: Mathieu Serandour <mathieu.serandour@telecom-paris.fr>
Date: Mon, 30 Jan 2023 16:06:20 +0100
Subject: [PATCH] add missing RVFI signals to picorv32_axi and picorv32_wb

---
 picorv32.v | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/picorv32.v b/picorv32.v
index cfc7ce0..9d3f9b2 100644
--- a/picorv32.v
+++ b/picorv32.v
@@ -2584,6 +2584,8 @@ module picorv32_axi #(
 	output        rvfi_trap,
 	output        rvfi_halt,
 	output        rvfi_intr,
+	output [ 1:0] rvfi_mode,
+	output [ 1:0] rvfi_ixl,
 	output [ 4:0] rvfi_rs1_addr,
 	output [ 4:0] rvfi_rs2_addr,
 	output [31:0] rvfi_rs1_rdata,
@@ -2597,6 +2599,14 @@ module picorv32_axi #(
 	output [ 3:0] rvfi_mem_wmask,
 	output [31:0] rvfi_mem_rdata,
 	output [31:0] rvfi_mem_wdata,
+	output reg [63:0] rvfi_csr_mcycle_rmask,
+	output reg [63:0] rvfi_csr_mcycle_wmask,
+	output reg [63:0] rvfi_csr_mcycle_rdata,
+	output reg [63:0] rvfi_csr_mcycle_wdata,
+	output reg [63:0] rvfi_csr_minstret_rmask,
+	output reg [63:0] rvfi_csr_minstret_wmask,
+	output reg [63:0] rvfi_csr_minstret_rdata,
+	output reg [63:0] rvfi_csr_minstret_wdata,
 `endif
 
 	// Trace Interface
@@ -2698,6 +2708,8 @@ module picorv32_axi #(
 		.rvfi_trap     (rvfi_trap     ),
 		.rvfi_halt     (rvfi_halt     ),
 		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_mode     (rvfi_mode     ),
+		.rvfi_ixl      (rvfi_ixl      ),
 		.rvfi_rs1_addr (rvfi_rs1_addr ),
 		.rvfi_rs2_addr (rvfi_rs2_addr ),
 		.rvfi_rs1_rdata(rvfi_rs1_rdata),
@@ -2711,6 +2723,14 @@ module picorv32_axi #(
 		.rvfi_mem_wmask(rvfi_mem_wmask),
 		.rvfi_mem_rdata(rvfi_mem_rdata),
 		.rvfi_mem_wdata(rvfi_mem_wdata),
+		.rvfi_csr_mcycle_rmask  (rvfi_csr_mcycle_rmask),
+		.rvfi_csr_mcycle_wmask  (rvfi_csr_mcycle_wmask),
+		.rvfi_csr_mcycle_rdata  (rvfi_csr_mcycle_rdata),
+		.rvfi_csr_mcycle_wdata  (rvfi_csr_mcycle_wdata),
+		.rvfi_csr_minstret_rmask(rvfi_csr_minstret_rmask),
+		.rvfi_csr_minstret_wmask(rvfi_csr_minstret_wmask),
+		.rvfi_csr_minstret_rdata(rvfi_csr_minstret_rdata),
+		.rvfi_csr_minstret_wdata(rvfi_csr_minstret_wdata),
 `endif
 
 		.trace_valid(trace_valid),
@@ -2870,6 +2890,8 @@ module picorv32_wb #(
 	output        rvfi_trap,
 	output        rvfi_halt,
 	output        rvfi_intr,
+	output reg [ 1:0] rvfi_mode,
+	output reg [ 1:0] rvfi_ixl,
 	output [ 4:0] rvfi_rs1_addr,
 	output [ 4:0] rvfi_rs2_addr,
 	output [31:0] rvfi_rs1_rdata,
@@ -2883,6 +2905,14 @@ module picorv32_wb #(
 	output [ 3:0] rvfi_mem_wmask,
 	output [31:0] rvfi_mem_rdata,
 	output [31:0] rvfi_mem_wdata,
+	output reg [63:0] rvfi_csr_mcycle_rmask,
+	output reg [63:0] rvfi_csr_mcycle_wmask,
+	output reg [63:0] rvfi_csr_mcycle_rdata,
+	output reg [63:0] rvfi_csr_mcycle_wdata,
+	output reg [63:0] rvfi_csr_minstret_rmask,
+	output reg [63:0] rvfi_csr_minstret_wmask,
+	output reg [63:0] rvfi_csr_minstret_rdata,
+	output reg [63:0] rvfi_csr_minstret_wdata,
 `endif
 
 	// Trace Interface
@@ -2962,6 +2992,8 @@ module picorv32_wb #(
 		.rvfi_trap     (rvfi_trap     ),
 		.rvfi_halt     (rvfi_halt     ),
 		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_mode     (rvfi_mode     ),
+		.rvfi_ixl      (rvfi_ixl      ),
 		.rvfi_rs1_addr (rvfi_rs1_addr ),
 		.rvfi_rs2_addr (rvfi_rs2_addr ),
 		.rvfi_rs1_rdata(rvfi_rs1_rdata),
@@ -2975,6 +3007,14 @@ module picorv32_wb #(
 		.rvfi_mem_wmask(rvfi_mem_wmask),
 		.rvfi_mem_rdata(rvfi_mem_rdata),
 		.rvfi_mem_wdata(rvfi_mem_wdata),
+		.rvfi_csr_mcycle_rmask(rvfi_csr_mcycle_rmask),
+		.rvfi_csr_mcycle_wmask(rvfi_csr_mcycle_wmask),
+		.rvfi_csr_mcycle_rdata(rvfi_csr_mcycle_rdata),
+		.rvfi_csr_mcycle_wdata(rvfi_csr_mcycle_wdata),
+		.rvfi_csr_minstret_rmask(rvfi_csr_minstret_rmask),
+		.rvfi_csr_minstret_wmask(rvfi_csr_minstret_wmask),
+		.rvfi_csr_minstret_rdata(rvfi_csr_minstret_rdata),
+		.rvfi_csr_minstret_wdata(rvfi_csr_minstret_wdata),
 `endif
 
 		.trace_valid(trace_valid),