From df1ae479e368af5065c7d45e97a2a8c9b46b7dc4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 10 Apr 2016 13:39:39 +0200
Subject: [PATCH] Support mem_la interface in torture test

---
 scripts/torture/.gitignore  |  1 +
 scripts/torture/Makefile    |  2 +-
 scripts/torture/test.sh     |  2 +-
 scripts/torture/testbench.v | 71 +++++++++++++++++++++++++++++--------
 4 files changed, 60 insertions(+), 16 deletions(-)

diff --git a/scripts/torture/.gitignore b/scripts/torture/.gitignore
index a9db520..9cae116 100644
--- a/scripts/torture/.gitignore
+++ b/scripts/torture/.gitignore
@@ -10,3 +10,4 @@ test.bin
 test.hex
 test.ref
 test.vvp
+test.vcd
diff --git a/scripts/torture/Makefile b/scripts/torture/Makefile
index 38051f0..946efdd 100644
--- a/scripts/torture/Makefile
+++ b/scripts/torture/Makefile
@@ -82,7 +82,7 @@ loop:
 
 clean:
 	rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests obj_dir
-	rm -f test.S test.elf test.bin test.hex test.ref test.vvp
+	rm -f test.S test.elf test.bin test.hex test.ref test.vvp test.vcd
 
 .PHONY: test batch loop clean
 
diff --git a/scripts/torture/test.sh b/scripts/torture/test.sh
index c385616..aa31fea 100644
--- a/scripts/torture/test.sh
+++ b/scripts/torture/test.sh
@@ -24,5 +24,5 @@ python3 ../../firmware/makehex.py test.bin 4096 > test.hex
 ## Run test
 
 iverilog -o test.vvp testbench.v ../../picorv32.v
-vvp test.vvp +hex=test.hex +ref=test.ref
+vvp test.vvp +vcd +hex=test.hex +ref=test.ref
 
diff --git a/scripts/torture/testbench.v b/scripts/torture/testbench.v
index 088b7aa..8327bce 100644
--- a/scripts/torture/testbench.v
+++ b/scripts/torture/testbench.v
@@ -18,19 +18,45 @@ module testbench (
 	wire [3:0]  mem_wstrb;
 	reg  [31:0] mem_rdata;
 
+	wire        mem_la_read;
+	wire        mem_la_write;
+	wire [31:0] mem_la_addr;
+	wire [31:0] mem_la_wdata;
+	wire [3:0]  mem_la_wstrb;
+
+	reg [31:0] x32 = 314159265;
+	reg [31:0] next_x32;
+
+	always @(posedge clk) begin
+		if (resetn) begin
+			next_x32 = x32;
+			next_x32 = next_x32 ^ (next_x32 << 13);
+			next_x32 = next_x32 ^ (next_x32 >> 17);
+			next_x32 = next_x32 ^ (next_x32 << 5);
+			x32 <= next_x32;
+		end
+	end
+
 	picorv32 #(
 		.COMPRESSED_ISA(1)
 	) uut (
 		.clk         (clk         ),
 		.resetn      (resetn      ),
 		.trap        (trap        ),
+
 		.mem_valid   (mem_valid   ),
 		.mem_instr   (mem_instr   ),
 		.mem_ready   (mem_ready   ),
 		.mem_addr    (mem_addr    ),
 		.mem_wdata   (mem_wdata   ),
 		.mem_wstrb   (mem_wstrb   ),
-		.mem_rdata   (mem_rdata   )
+		.mem_rdata   (mem_rdata   ),
+
+		.mem_la_read (mem_la_read ),
+		.mem_la_write(mem_la_write),
+		.mem_la_addr (mem_la_addr ),
+		.mem_la_wdata(mem_la_wdata),
+		.mem_la_wstrb(mem_la_wstrb)
 	);
 
 	localparam integer filename_len = 18;
@@ -45,8 +71,12 @@ module testbench (
 	initial begin
 		if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory);
 		if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref);
-		// $dumpfile("testbench.vcd");
-		// $dumpvars(0, testbench);
+`ifndef VERILATOR
+		if ($test$plusargs("vcd")) begin
+			$dumpfile("test.vcd");
+			$dumpvars(0, testbench);
+		end
+`endif
 	end
 
 	always @(posedge clk) begin
@@ -54,15 +84,28 @@ module testbench (
 		mem_rdata <= 'bx;
 
 		if (!trap || !resetn) begin
-			if (mem_valid && !mem_ready && resetn) begin
-				mem_ready <= 1;
-				if (mem_wstrb) begin
-					if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
-					if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
-					if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
-					if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
-				end else begin
-					mem_rdata <= memory[mem_addr >> 2];
+			if (x32[0] && resetn) begin
+				if (mem_la_read) begin
+					mem_ready <= 1;
+					mem_rdata <= memory[mem_la_addr >> 2];
+				end else
+				if (mem_la_write) begin
+					mem_ready <= 1;
+					if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
+					if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
+					if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
+					if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
+				end else
+				if (mem_valid && !mem_ready) begin
+					mem_ready <= 1;
+					if (mem_wstrb) begin
+						if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
+						if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
+						if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
+						if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
+					end else begin
+						mem_rdata <= memory[mem_addr >> 2];
+					end
 				end
 			end
 		end else begin
@@ -74,9 +117,9 @@ module testbench (
 				end
 			end
 			if (errcount)
-				$display("FAILED: Got %1d errors for %s => %s!", errcount, hex_filename, ref_filename);
+				$display("FAILED: Got %1d errors for %1s => %1s!", errcount, hex_filename, ref_filename);
 			else
-				$display("PASSED %s => %s.", hex_filename, ref_filename);
+				$display("PASSED %1s => %1s.", hex_filename, ref_filename);
 			$finish;
 		end