From f4bb91b060211884fc0b85479fb6becf20daeb1f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 Jun 2016 10:46:52 +0200 Subject: [PATCH] RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" --- README.md | 16 ++++++++-------- dhrystone/start.S | 4 ++-- dhrystone/stdlib.c | 2 +- firmware/irq.c | 6 +++--- firmware/multest.c | 2 +- firmware/sieve.c | 2 +- firmware/start.S | 6 +++--- picorv32.v | 30 +++++++++++++++--------------- scripts/csmith/syscalls.c | 4 ++-- scripts/cxxdemo/syscalls.c | 4 ++-- scripts/icestorm/firmware.S | 2 +- scripts/icestorm/firmware.c | 2 +- scripts/torture/riscv_test.h | 4 ++-- scripts/vivado/firmware.S | 2 +- tests/riscv_test.h | 2 +- 15 files changed, 44 insertions(+), 44 deletions(-) diff --git a/README.md b/README.md index d3a7588..266eea1 100644 --- a/README.md +++ b/README.md @@ -215,9 +215,9 @@ accesses. Set this to 0 to disable the circuitry for catching illegal instructions. -The core will still trap on an `SBREAK` instruction with this option -set to 0. With IRQs enabled, an `SBREAK` normally triggers an IRQ 1. With -this option set to 0, an `SBREAK` will trap the processor without +The core will still trap on `EBREAK` instructions with this option +set to 0. With IRQs enabled, an `EBREAK` normally triggers an IRQ 1. With +this option set to 0, an `EBREAK` will trap the processor without triggering an interrupt. #### ENABLE_PCPI (default = 0) @@ -448,11 +448,11 @@ interrupt handler returns. The IRQs 0-2 can be triggered internally by the following built-in interrupt sources: -| IRQ | Interrupt Source | -| ---:| -----------------------------------| -| 0 | Timer Interrupt | -| 1 | SBREAK or Illegal Instruction | -| 2 | BUS Error (Unalign Memory Access) | +| IRQ | Interrupt Source | +| ---:| ------------------------------------| +| 0 | Timer Interrupt | +| 1 | EBREAK/ECALL or Illegal Instruction | +| 2 | BUS Error (Unalign Memory Access) | This interrupts can also be triggered by external sources, such as co-processors connected via PCPI. diff --git a/dhrystone/start.S b/dhrystone/start.S index 092ba96..9fb2359 100644 --- a/dhrystone/start.S +++ b/dhrystone/start.S @@ -46,6 +46,6 @@ start: sw a4,0(a0) sw a5,0(a0) - /* break */ - sbreak + /* trap */ + ebreak diff --git a/dhrystone/stdlib.c b/dhrystone/stdlib.c index 1b04026..b4d2a2f 100644 --- a/dhrystone/stdlib.c +++ b/dhrystone/stdlib.c @@ -36,7 +36,7 @@ char *malloc(int size) // printf("[malloc(%d) -> %d (%d..%d)]", size, (int)p, heap_memory_used, heap_memory_used + size); heap_memory_used += size; if (heap_memory_used > 1024) - asm("sbreak"); + asm("ebreak"); return p; } diff --git a/firmware/irq.c b/firmware/irq.c index aaa141d..13dcb57 100644 --- a/firmware/irq.c +++ b/firmware/irq.c @@ -30,7 +30,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs) else print_hex(instr, 4); print_str("\n"); - __asm__ volatile ("sbreak"); + __asm__ volatile ("ebreak"); } } @@ -62,7 +62,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs) if ((irqs & 2) != 0) { if (instr == 0x00100073 || instr == 0x9002) { - print_str("SBREAK instruction at 0x"); + print_str("EBREAK instruction at 0x"); print_hex(pc, 8); print_str("\n"); } else { @@ -132,7 +132,7 @@ uint32_t *irq(uint32_t *regs, uint32_t irqs) print_dec(timer_irq_count); print_str("\n"); - __asm__ volatile ("sbreak"); + __asm__ volatile ("ebreak"); } return regs; diff --git a/firmware/multest.c b/firmware/multest.c index 5b68555..93e48df 100644 --- a/firmware/multest.c +++ b/firmware/multest.c @@ -75,7 +75,7 @@ void multest(void) if (s_mul != h_mul || s_mulh != h_mulh || s_mulhsu != h_mulhsu || s_mulhu != h_mulhu) { print_str("ERROR!\n"); - __asm__ volatile ("sbreak"); + __asm__ volatile ("ebreak"); return; } diff --git a/firmware/sieve.c b/firmware/sieve.c index c31e942..ff945eb 100644 --- a/firmware/sieve.c +++ b/firmware/sieve.c @@ -78,7 +78,7 @@ void sieve(void) print_str(" OK\n"); } else { print_str(" ERROR\n"); - __asm__ volatile ("sbreak"); + __asm__ volatile ("ebreak"); } } diff --git a/firmware/start.S b/firmware/start.S index 403ac24..e256cac 100644 --- a/firmware/start.S +++ b/firmware/start.S @@ -260,7 +260,7 @@ irq_vec: // new irq_regs address returned from C code in a0 addi a1, zero, 0x200 beq a0, a1, 1f - sbreak + ebreak 1: #ifdef ENABLE_FASTIRQ @@ -478,8 +478,8 @@ start: sw a4,0(a0) sw a5,0(a0) - /* break */ - sbreak + /* trap */ + ebreak /* Hard mul functions for multest.c diff --git a/picorv32.v b/picorv32.v index cdfb65f..755bc04 100644 --- a/picorv32.v +++ b/picorv32.v @@ -97,7 +97,7 @@ module picorv32 #( output reg [31:0] eoi ); localparam integer irq_timer = 0; - localparam integer irq_sbreak = 1; + localparam integer irq_ebreak = 1; localparam integer irq_buserror = 2; localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; @@ -503,7 +503,7 @@ module picorv32 #( reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; - reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_scall_sbreak; + reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; wire instr_trap; @@ -919,7 +919,7 @@ module picorv32 #( instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; - instr_scall_sbreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || + instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; @@ -1273,11 +1273,11 @@ module picorv32 #( latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch; end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_scall_sbreak)) begin + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin pcpi_valid <= 0; - `debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin - next_irq_pending[irq_sbreak] = 1; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else cpu_state <= cpu_state_trap; @@ -1286,9 +1286,9 @@ module picorv32 #( cpu_state <= cpu_state_ld_rs2; end end else begin - `debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin - next_irq_pending[irq_sbreak] = 1; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else cpu_state <= cpu_state_trap; @@ -1423,11 +1423,11 @@ module picorv32 #( latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch; end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_scall_sbreak)) begin + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin pcpi_valid <= 0; - `debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin - next_irq_pending[irq_sbreak] = 1; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else cpu_state <= cpu_state_trap; @@ -1574,7 +1574,7 @@ module picorv32 #( end else cpu_state <= cpu_state_trap; end - if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_scall_sbreak) begin + if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin cpu_state <= cpu_state_trap; end diff --git a/scripts/csmith/syscalls.c b/scripts/csmith/syscalls.c index f12b07e..cdf872f 100644 --- a/scripts/csmith/syscalls.c +++ b/scripts/csmith/syscalls.c @@ -44,7 +44,7 @@ void unimplemented_syscall() const char *p = "Unimplemented system call called!\n"; while (*p) *(volatile int*)0x10000000 = *(p++); - asm volatile ("sbreak"); + asm volatile ("ebreak"); __builtin_unreachable(); } @@ -89,7 +89,7 @@ void *sbrk(ptrdiff_t incr) void _exit(int exit_status) { - asm volatile ("sbreak"); + asm volatile ("ebreak"); __builtin_unreachable(); } diff --git a/scripts/cxxdemo/syscalls.c b/scripts/cxxdemo/syscalls.c index f12b07e..cdf872f 100644 --- a/scripts/cxxdemo/syscalls.c +++ b/scripts/cxxdemo/syscalls.c @@ -44,7 +44,7 @@ void unimplemented_syscall() const char *p = "Unimplemented system call called!\n"; while (*p) *(volatile int*)0x10000000 = *(p++); - asm volatile ("sbreak"); + asm volatile ("ebreak"); __builtin_unreachable(); } @@ -89,7 +89,7 @@ void *sbrk(ptrdiff_t incr) void _exit(int exit_status) { - asm volatile ("sbreak"); + asm volatile ("ebreak"); __builtin_unreachable(); } diff --git a/scripts/icestorm/firmware.S b/scripts/icestorm/firmware.S index e6c6e42..d19783d 100644 --- a/scripts/icestorm/firmware.S +++ b/scripts/icestorm/firmware.S @@ -9,4 +9,4 @@ addi sp, sp, %lo(512) jal ra, main /* break */ -sbreak +ebreak diff --git a/scripts/icestorm/firmware.c b/scripts/icestorm/firmware.c index fcb5152..a5e5236 100644 --- a/scripts/icestorm/firmware.c +++ b/scripts/icestorm/firmware.c @@ -42,7 +42,7 @@ void gray(uint8_t c) uint8_t gray_decoded = gray_decode(gray_simple); if (gray_simple != gray_bitwise || gray_decoded != c) - while (1) asm volatile ("sbreak"); + while (1) asm volatile ("ebreak"); output(gray_simple); } diff --git a/scripts/torture/riscv_test.h b/scripts/torture/riscv_test.h index de1c069..36c5b54 100644 --- a/scripts/torture/riscv_test.h +++ b/scripts/torture/riscv_test.h @@ -7,7 +7,7 @@ #define RVTEST_DATA_BEGIN #define RVTEST_DATA_END -#define RVTEST_FAIL sbreak -#define RVTEST_PASS sbreak +#define RVTEST_FAIL ebreak +#define RVTEST_PASS ebreak #endif diff --git a/scripts/vivado/firmware.S b/scripts/vivado/firmware.S index ae554fb..c55a3ba 100644 --- a/scripts/vivado/firmware.S +++ b/scripts/vivado/firmware.S @@ -9,4 +9,4 @@ addi sp, sp, %lo(16*1024) jal ra, main /* break */ -sbreak +ebreak diff --git a/tests/riscv_test.h b/tests/riscv_test.h index 6c0eb80..be033fd 100644 --- a/tests/riscv_test.h +++ b/tests/riscv_test.h @@ -55,7 +55,7 @@ TEST_FUNC_NAME: \ sw a3,0(a0); \ sw a2,0(a0); \ sw a4,0(a0); \ - sbreak; + ebreak; #define RVTEST_CODE_END #define RVTEST_DATA_BEGIN .balign 4;