From 70ea50e60dbb9dc13835f0c7c34b0015e0513196 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Sun, 4 Mar 2018 21:20:29 +0100
Subject: [PATCH 1/2] Add verilator testbench

---
 testbench.cc | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 testbench.cc

diff --git a/testbench.cc b/testbench.cc
new file mode 100644
index 0000000..81c6273
--- /dev/null
+++ b/testbench.cc
@@ -0,0 +1,27 @@
+#include "Vpicorv32_wrapper.h"
+#include "verilated_vcd_c.h"
+
+int main(int argc, char **argv, char **env)
+{
+	Verilated::commandArgs(argc, argv);
+	Verilated::traceEverOn(true);
+	Vpicorv32_wrapper* top = new Vpicorv32_wrapper;
+
+	VerilatedVcdC* tfp = new VerilatedVcdC;
+	top->trace (tfp, 99);
+        tfp->open ("testbench.vcd");
+	top->clk = 0;
+	int t = 0;
+	while (!Verilated::gotFinish()) {
+		if (t > 200)
+			top->resetn = 1;
+		top->clk = !top->clk;
+		top->eval();
+		tfp->dump (t);
+		t += 5;
+	}
+	tfp->close();
+	delete top;
+	exit(0);
+}
+

From 6c5579b49053acb9da95961d319ef275852b6b16 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Sun, 4 Mar 2018 21:22:03 +0100
Subject: [PATCH 2/2] Add FuseSoC core file

---
 picorv32.core | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 picorv32.core

diff --git a/picorv32.core b/picorv32.core
new file mode 100644
index 0000000..08ee704
--- /dev/null
+++ b/picorv32.core
@@ -0,0 +1,78 @@
+CAPI=2:
+name : ::picorv32:0-r1
+
+filesets:
+  rtl:
+    files: [picorv32.v]
+    file_type : verilogSource
+  tb:
+    files: [testbench.v]
+    file_type : verilogSource
+    depend:
+  tb_ez:
+    files: [testbench_ez.v]
+    file_type : verilogSource
+  tb_wb:
+    files: [testbench_wb.v]
+    file_type : verilogSource
+  tb_verilator:
+    files:
+      - testbench.cc : {file_type : cppSource}
+
+targets:
+  default:
+    filesets: [rtl]
+  lint:
+    filesets: [rtl]
+    default_tool : verilator
+    tools:
+      verilator:
+        mode : lint-only
+    toplevel : [picorv32_axi]
+  test:
+    default_tool: icarus
+    filesets: [rtl, tb, "tool_verilator? (tb_verilator)"]
+    parameters: [COMPRESSED_ISA, axi_test, firmware, noerror, trace, vcd, verbose]
+    toplevel:
+      - "tool_verilator?  (picorv32_wrapper)"
+      - "!tool_verilator? (testbench)"
+      
+    tools:
+      verilator :
+        cli_parser : fusesoc
+        mode : cc
+        verilator_options : [-Wno-fatal, --trace]
+  test_ez:
+    default_tool: icarus
+    filesets: [rtl, tb_ez]
+    parameters: [vcd]
+    toplevel: [testbench]
+  test_wb:
+    default_tool: icarus
+    filesets: [rtl, tb_wb]
+    parameters: [COMPRESSED_ISA, firmware, noerror, trace, vcd]
+    toplevel: [testbench]
+
+parameters:
+  COMPRESSED_ISA:
+    datatype  : str
+    default   : 1
+    paramtype : vlogdefine
+  axi_test:
+    datatype  :  bool
+    paramtype : plusarg
+  firmware:
+    datatype  :  file
+    paramtype : plusarg
+  noerror:
+    datatype  :  bool
+    paramtype : plusarg
+  trace:
+    datatype  : bool
+    paramtype : plusarg
+  vcd:
+    datatype  : bool
+    paramtype : plusarg
+  verbose:
+    datatype : bool
+    paramtype : plusarg