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picorv32
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610 Commits 2 Branches 1 Tag 2.8 MiB
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610 Commits

Author SHA1 Message Date
Clifford Wolf 0ab0b6eca4 Added z3 support to mem_equiv.py 2015-08-14 23:57:09 +02:00
Clifford Wolf 16f97a86a1 Reset bugfix (bug found via scripts/smt2-bmc/mem_equiv.*) 2015-08-13 13:30:21 +02:00
Clifford Wolf 8397962424 Progress with smt2-based bmc scripts 2015-08-13 11:52:53 +02:00
Clifford Wolf 12e64c7968 Progress with smt2-based bmc scripts 2015-08-10 12:11:33 +02:00
Clifford Wolf 93d78f38d8 Added smt2-based bmc scripts 2015-08-09 14:23:02 +02:00
Clifford Wolf 2f326d0761 Improvements in icestorm test firmware 2015-07-31 11:08:28 +02:00
Clifford Wolf 484fa4ac5f icestorm sim improvements 2015-07-21 17:43:33 +02:00
Clifford Wolf f4842be8bb Improved icestorm example 2015-07-19 16:44:31 +02:00
Clifford Wolf 6c7125b380 Improved icestorm example 2015-07-19 16:09:19 +02:00
Clifford Wolf 812d4d0793 Added $(VIVADO_BASE) to vivado Makefile 2015-07-16 18:59:58 +02:00
Clifford Wolf d8c3157bf8 Improved firmware for vivado "system" example 2015-07-16 11:11:45 +02:00
Clifford Wolf 0249d538fa Improved vivado "system" example 2015-07-12 22:59:21 +02:00
Clifford Wolf 94edf3565d Vivado "system" example 2015-07-09 02:48:14 +02:00
Clifford Wolf 2a04d0e52e Updated evaluation 2015-07-09 00:57:14 +02:00
Clifford Wolf bf7f984d42 Refactoring of TWO_CYCLE_ALU 2015-07-08 23:15:14 +02:00
Clifford Wolf 51be282633 Updated evaluation 2015-07-08 22:31:03 +02:00
Clifford Wolf dd30b57ea6 Added TWO_CYCLE_ALU parameter 2015-07-08 20:17:03 +02:00
Clifford Wolf a97a715987 Enabled report_timing in vivado synth_area scripts 2015-07-08 10:16:10 +02:00
Clifford Wolf bd1cc3466f Updated eval data 2015-07-08 09:48:42 +02:00
Clifford Wolf b6c4c2eeb9 Added TWO_CYCLE_COMPARE 2015-07-07 22:51:52 +02:00
Clifford Wolf 54f89ba904 Updated RV32I tools instructions 2015-07-05 10:32:26 +02:00
Clifford Wolf 8d404182b3 Improved IceStorm example script 2015-07-04 16:34:18 +02:00
Clifford Wolf 4601fa23e9 Added -Werror 2015-07-04 16:31:26 +02:00
Clifford Wolf 21da66db68 c++/c99-style for loops in firmware 2015-07-04 11:47:43 +02:00
Clifford Wolf 91f75bdf1f Turned gcc warnings up to eleven 
Patch by Larry Doolittle
 2015-07-04 11:47:19 +02:00
Clifford Wolf 2df7aadc7a Fixed typo in Makefile 2015-07-03 18:43:37 +02:00
Clifford Wolf 9c028fc965 Added missing LD_RS1 debug statements 2015-07-02 14:51:28 +02:00
Clifford Wolf 686f77facb Updated area and timing stats 2015-07-02 14:41:15 +02:00
Clifford Wolf ab503d5756 Being more aggressive with parallel cases 2015-07-02 12:55:05 +02:00
Clifford Wolf c10125eb5c Added TWO_STAGE_SHIFT parameter 2015-07-02 12:29:06 +02:00
Clifford Wolf 853ce91300 Added `debug macro 2015-07-02 12:17:45 +02:00
Clifford Wolf 476046c177 Minor Makefile changes 2015-07-02 11:01:21 +02:00
Clifford Wolf b6e8c15901 Removed trailing whitespaces in dhrystone code 2015-07-02 10:50:54 +02:00
Clifford Wolf c48a3b2434 Removed trailing whitespaces 2015-07-02 10:49:35 +02:00
Clifford Wolf 084056f729 Unsigned arguments for print_dec() 
Patch by Larry Doolittle
 2015-07-02 10:46:21 +02:00
Clifford Wolf a7f9b7fbf3 Some testbench-related improvements 
Patch by Larry Doolittle
 2015-07-02 10:45:35 +02:00
Clifford Wolf 9d3b0a9692 Updated evaluation 2015-07-02 00:54:11 +02:00
Clifford Wolf 198c995c8f Back to Vivado 2015.1 
my synthesis license has a 2015.05 version limit..
 2015-07-01 22:42:25 +02:00
Clifford Wolf 84e2202fef Vivado 2015.2 area evaluation 2015-07-01 22:18:20 +02:00
Clifford Wolf e72abc0284 Added vivado synth_area_{small,regular,large}.tcl scripts 2015-07-01 21:51:15 +02:00
Clifford Wolf 553b1ef143 Updated Xilinx 7-Series area stats 2015-07-01 21:48:51 +02:00
Clifford Wolf 34193bf9df Added CATCH_MISALIGN and CATCH_ILLINSN 2015-07-01 21:20:51 +02:00
Clifford Wolf f6fe27ecbf After some profiling: one-hot FSM encoding 2015-07-01 21:20:31 +02:00
Clifford Wolf c22ea8fe0a Spelling fixes by Larry Doolittle 2015-07-01 08:18:10 +02:00
Clifford Wolf 4a9fda0737 Improvements in PCPI MUL core 2015-06-30 16:51:26 +02:00
Clifford Wolf 9d809eb0d9 Added TOC to README 2015-06-30 12:25:05 +02:00
Clifford Wolf 997c5ce341 Added "make test_synth" 2015-06-30 01:46:25 +02:00
Clifford Wolf 56b2b4971d Added Note about Icarus Verilog to README 2015-06-29 09:58:39 +02:00
Clifford Wolf 7417a3e249 Added LATCHED_IRQ parameter 2015-06-29 07:54:47 +02:00
Clifford Wolf 1321840665 Minor README change 2015-06-29 07:37:48 +02:00