From 0781716a9e440c6324e5bb9d3f405b1570d95c0e Mon Sep 17 00:00:00 2001
From: Emilio Rojas <emilio93@gmail.com>
Date: Wed, 10 Oct 2018 13:26:48 -0600
Subject: [PATCH] Add instructions for nexys 4 ddr board

---
 ...-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md

diff --git a/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md b/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md
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+++ b/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md
@@ -0,0 +1,56 @@
+> *This instructions are directed towards the Nexys 4 DDR board which has an Artix 7 FPGA, specifically XC7A100T-1CSG324C, however the instructions can be adapted to work on other boards programmed through vivado.*
+
+First of all you will need Vivado, follow the instructions at https://reference.digilentinc.com/vivado/installing-vivado/start to install the software plus board support.
+
+Then you will need to update two files in order to synthesize, implement and generate the bitstream.
+
+First update [scripts/vivado/synth_system.tcl](scripts/vivado/synth_system.tcl). Change the following line:
+
+```
+synth_design -part xc7a100tcsg324-1 -top system
+```
+to
+```
+synth_design -part xc7a100tcsg324-1 -top system
+```
+in order to update the target device to the FPGA in the Nexys 4 DDR board.
+
+Then update [scripts/vivado/synth_system.xcd](scripts/vivado/synth_system.xcd). Use
+
+```
+# XDC File for Nexys 4 DDR Board
+###########################
+
+set_property PACKAGE_PIN D5 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.00 [get_ports clk]
+
+# Pmod Header JA (JA0..JA7)
+set_property PACKAGE_PIN K1 [get_ports {out_byte[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
+set_property PACKAGE_PIN J3 [get_ports {out_byte[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
+set_property PACKAGE_PIN J2 [get_ports {out_byte[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
+set_property PACKAGE_PIN G2 [get_ports {out_byte[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
+set_property PACKAGE_PIN H1 [get_ports {out_byte[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
+set_property PACKAGE_PIN K2 [get_ports {out_byte[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
+set_property PACKAGE_PIN H2 [get_ports {out_byte[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
+set_property PACKAGE_PIN G3 [get_ports {out_byte[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]
+
+# Pmod Header JB (JB0..JB2)
+set_property PACKAGE_PIN A14 [get_ports {resetn}]
+set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
+set_property PACKAGE_PIN A16 [get_ports {trap}]
+set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
+set_property PACKAGE_PIN B14 [get_ports {out_byte_en}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]
+```
+Note this is basically the same file, what has changed are a few ports that in the xc7a100tcsg324-1 device are disabled(reserved for ground pins or nonexistent), you might want to rearrange the pins.
+
+Now in vivado go to Tools>Run Tcl Script..., make sure the Tcl Console working directory is in [scripts/vivado](scripts/vivado).
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