From c28ff9b717ae38a7a87e02cb20a646d695aeb7da Mon Sep 17 00:00:00 2001 From: Emilio Rojas Date: Wed, 10 Oct 2018 13:28:23 -0600 Subject: [PATCH] Updated Programming the Nexys 4 DDR Artix 7 FPGA Trainer Board (markdown) --- Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md b/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md index 213171f..e03e418 100644 --- a/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md +++ b/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md @@ -7,7 +7,7 @@ Then you will need to update two files in order to synthesize, implement and gen First update [scripts/vivado/synth_system.tcl](scripts/vivado/synth_system.tcl). Change the following line: ``` -synth_design -part xc7a100tcsg324-1 -top system +synth_design -part xc7k70t-fbg676 -top system ``` to ```