Hardware
/
picorv32
mirror of https://github.com/YosysHQ/picorv32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updated Programming the Nexys 4 DDR Artix 7 FPGA Trainer Board (markdown)

Emilio Rojas 2018-10-10 13:28:23 -06:00
parent d255a7252d
commit c28ff9b717
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board.md

@ -7,7 +7,7 @@ Then you will need to update two files in order to synthesize, implement and gen
First update [scripts/vivado/synth_system.tcl](scripts/vivado/synth_system.tcl). Change the following line: First update [scripts/vivado/synth_system.tcl](scripts/vivado/synth_system.tcl). Change the following line:
``` ```
synth_design -part xc7a100tcsg324-1 -top system synth_design -part xc7k70t-fbg676 -top system
``` ```
to to
``` ```