67 lines
1.6 KiB
Plaintext
67 lines
1.6 KiB
Plaintext
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m4_changequote(`⟨', `⟩')
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m4_changecom(⟨/*⟩, ⟨*/⟩)
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/* Copyright 2024 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*
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* BRAM to Wishbone interface.
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*/
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module bram_interface #(
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/* This is the last INDEX of the word array, which is indexed in
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* words, not octets. */
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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/* Width of the memory bus */
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parameter BUS_WID = 32,
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/* Width of a request. */
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parameter WORD_WID = 32,
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/* Bitmask used to extract the RAM location in the buffer. */
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parameter ADDR_MASK = 32'h1FFF
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) (
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input clk,
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input wb_cyc,
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input wb_stb,
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input wb_we,
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input [4-1:0] wb_sel,
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input [BUS_WID-1:0] wb_addr,
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input [BUS_WID-1:0] wb_data_i,
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output reg wb_ack,
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output wb_stall,
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output reg [BUS_WID-1:0] wb_data_o,
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);
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assign wb_stall = wb_ack;
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reg [BUS_WID-1:0] buffer [WORD_AMNT:0];
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m4_define(⟨bufwrite⟩, ⟨begin
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buffer[mem_addr & ADDR_MASK] <=
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(buffer[wb_addr & ADDR_MASK] & $1)
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| wb_data_i[$2];
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end⟩)
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always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack)
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if (!wb_we) begin
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wb_data_o <= buffer[wb_addr & ADDR_MASK];
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wb_ack <= 1;
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end else begin
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wb_ack <= 1;
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case (wb_sel)
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4'b1111: buffer[wb_addr & ADDR_MASK] <= wb_data_o;
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4'b0001: bufwrite(32'hFFFFFF00, 7:0)
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4'b0010: bufwrite(32'hFFFF00FF, 15:8)
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4'b0011: bufwrite(32'hFFFF0000, 15:0)
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4'b0100: bufwrite(32'hFF00FFFF, 23:16)
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4'b1000: bufwrite(32'h00FFFFFF, 31:24)
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4'b1100: bufwrite(32'h0000FFFF, 31:16)
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default: mem_ready <= 1;
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endcase
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end
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else if (!wb_stb) begin
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wb_ack <= 0;
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end
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endmodule
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