43 lines
762 B
Coq
43 lines
762 B
Coq
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module top
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#(
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parameter ADC_WID = 18,
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parameter DAC_WID = 24,
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parameter ADC_POLARITY = 1,
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parameter ADC_PHASE = 0,
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parameter DAC_DATA_WID = 20,
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parameter CONSTS_WID = 48,
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parameter DELAY_WID = 16
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(
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input clk,
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input signed [ADC_WID-1:0] read_data,
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output signed [DAC_WID-1:0] write_data,
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input signed [ADC_WID-1:0] setpt,
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input signed [CONSTS_WID-1:0] alpha,
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input signed [CONSTS_WID-1:0] cl_p,
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input [DELAY_WID-1:0] dy,
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output signed [ADC_WID:0] err,
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output signed [CONSTS_WID-1:0] adj
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);
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wire adc_sck;
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wire adc_ss;
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wire adc_mosi;
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spi_slave_no_write #(
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.WID(ADC_WID),
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.WID(5),
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.
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control_loop #(
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.ADC_WID(ADC_WID),
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.DAC_WID(DAC_WID),
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.DAC_DATA_WID(DAC_DATA_WID),
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.CONSTS_WID(CONSTS_WID),
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.DELAY_WID(DELAY_WID)
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) cloop (
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);
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endmodule
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