60 lines
1.7 KiB
C++
60 lines
1.7 KiB
C++
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#include "bram_dma.hpp"
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#include "../util.hpp"
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#include <cstdlib>
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BRAM_DMA_Sim::BRAM_DMA_Sim(uint32_t _start_addr,
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size_t _word_amnt,
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size_t _timer_max) {
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my_assert(_start_addr / 4 == 0, "start addr %d not 16 bit aligned",
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_start_addr);
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start_addr = _start_addr;
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word_amnt = _word_amnt;
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timer_max = _timer_max;
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ram = new uint32_t[word_amnt];
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}
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BRAM_DMA_SIM::~BRAM_DMA_Sim() {
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delete[] ram;
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}
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void BRAM_DMA_Sim::generate_random_data() {
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for (size_t i = 0; i < word_amnt; i++) {
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ram[i] = mask_extend(rand(), 20);
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}
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}
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void BRAM_DMA_Sim::execute_ram_access(uint32_t ram_dma_addr,
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uint32_t &ram_word,
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uint32_t &ram_valid) {
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ram_valid = 1;
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my_assert(ram_dma_addr < start_addr
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|| ram_dma_addr >= start_addr + word_amnt*4,
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"bad address %x\n", ram_dma_addr);
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my_assert(ram_dma_addr >= start_addr, "left oob access %x",
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tb->mod.ram_dma_addr);
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my_assert(ram_dma_addr < start_addr + WORD_AMNT*4,
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"right oob access %x", ram_dma_addr);
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my_assert(ram_dma_addr % 2 == 0, "unaligned access %x",
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ram_dma_addr);
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const auto addr = (ram_dma_addr - start_addr) / 4;
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if (tb->mod.ram_dma_addr % 4 == 0) {
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ram_word = ram_refresh_data[addr] & 0xFFFF;
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} else {
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ram_word = ram_refresh_data[addr] >> 16;
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}
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}
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void BRAM_DMA_Sim::posedge(uint32_t ram_dma_addr, uint32_t &ram_word,
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uint32_t ram_read, uint32_t &ram_valid) {
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if (ram_read && timer < timer_max) {
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timer++;
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if (timer == timer_max)
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execute_ram_access(ram_dma_addr, ram_word, ram_valid);
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} else {
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ram_valid = 0;
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timer = 0;
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}
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}
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