upsilon/firmware/rtl/control_loop/control_loop_cmds.vh

`define CONTROL_LOOP_NOOP 0
`define CONTROL_LOOP_STATUS 1
`define CONTROL_LOOP_SETPT 2
`define CONTROL_LOOP_P 3
`define CONTROL_LOOP_I 4
`define CONTROL_LOOP_ERR 5
`define CONTROL_LOOP_Z 6
`define CONTROL_LOOP_CYCLES 7
`define CONTROL_LOOP_DELAY 8
`define CONTROL_LOOP_CMD_WIDTH 8
`define CONTROL_LOOP_WRITE_BIT (1 << (`CONTROL_LOOP_CMD_WIDTH-1))
add write-read interface to control loop 2022-10-18 07:10:06 -04:00			`define CONTROL_LOOP_NOOP 0
			`define CONTROL_LOOP_STATUS 1
			`define CONTROL_LOOP_SETPT 2
			`define CONTROL_LOOP_P 3
more work on control_loop * Make SPI masters internal to control loop module * Rename commands to use I isntead of alpha * add ADC value -> DAC value conversion to control loop math 2022-11-18 19:11:56 -05:00			`define CONTROL_LOOP_I 4
add write-read interface to control loop 2022-10-18 07:10:06 -04:00			`define CONTROL_LOOP_ERR 5
write total value to dac, not adjustment vlaue 2022-10-20 15:42:24 -04:00			`define CONTROL_LOOP_Z 6
add cycle count for each iteration 2022-10-23 14:21:31 -04:00			`define CONTROL_LOOP_CYCLES 7
control loop simulator passes lint 2022-11-21 21:41:50 -05:00			`define CONTROL_LOOP_DELAY 8
add write-read interface to control loop 2022-10-18 07:10:06 -04:00			`define CONTROL_LOOP_CMD_WIDTH 8
control loop simulator passes lint 2022-11-21 21:41:50 -05:00			`define CONTROL_LOOP_WRITE_BIT (1 << (`CONTROL_LOOP_CMD_WIDTH-1))