upsilon/firmware/Makefile

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Makefile
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.PHONY: cpu clean rtl_codegen
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DEVICETREE_GEN_DIR=.
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all: rtl_codegen build/digilent_arty/digilent_arty.bit overlay.dts overlay.cmake pin_io.h
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rtl_codegen:
cd rtl && make
build/digilent_arty/digilent_arty.bit: rtl_codegen soc.py
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python3 soc.py
clean:
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rm -rf build csr.json overlay.config overlay.dts pin_io.h
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overlay.dts overlay.cmake: csr.json litex_json2dts_zephyr.py
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# NOTE: Broken in LiteX 2022.4.
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$(DEVICETREE_GEN_DIR)/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.cmake csr.json
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pin_io.h: csr.json generate_csr_locations.py
python3 generate_csr_locations.py > pin_io.h